MAS6502 datasheet(11/20 Pages) MAS

11 / 20 page

DA6502.008

29 November 2012

11 (20)

SERIAL DATA INTERFACE (I

BUS) CONTROL

Serial Interface

MAS6502 has an I

® bus compatible two wire

serial data interface comprising of serial clock

(SCL) and bi-directional serial data (SDA) pins. Both

the SCL & SDA lines, in the I

® bus, are of open-

drain design, thus, external pull-up resistors are

needed.

The serial data interface is used to configure and

start the A/D conversion and read the measurement

result when the A/D conversion has been finished.

The digital interface includes also end of conversion

(EOC) and master reset (XCLR) pins. The EOC

goes high when the A/D conversion has finished.

The XCLR signal is active low and used to reset the

A/D

converter.

reset

initializes

the

serial

communication bus and sets internal registers and

counters to value 00HEX. After connecting the supply

voltage to MAS6502, and before starting operating

the device via the serial bus, it is required to reset

the device with the XCLR reset pin or using reset

been longer than 400 ns. If the supply voltage rise

time is shorter than this making an external reset is

not necessary since the device is automatically

reset by the power on reset (POR) circuitry. It is

however recommended to use the XCLR reset

feature to solve unexpected error state conditions.

The XCLR pin can be left unconnected when not

used. It has internal pull up to VDD. See Electrical

Characteristics for the XCLR Pin Pull Up Current.

Device Address

The I

® bus definition allows several I2C® bus

devices to be connected to the same bus. The

devices are distinguished from each other by unique

device address codes. MAS6502 device address is

shown in table 7. The LSB bit of the device address

defines whether the bus is configured for Read (1)

or Write (0) operation.

Table 7. MAS6502 device address

W/R

0/1

Bus Protocol Definitions

Data transfer is initiated with a Start bit (S) when

SDA is pulled low while SCL stays high. Then, SDA

sets the transferred bit while SCL is low and the

data is sampled (received) when SCL rises. When

the transfer is complete, a Stop bit (P) is sent by

releasing the data line to allow it to be pulled up

while SCL is constantly high.

Figure 3 shows the start (S) and stop (P) bits and a

data bit. Data must be held stable at the SDA pin

when SCL is high. Data at the SDA pin can change

value only when SCL is low.

Each SDA line byte must contain 8-bits when the

most significant bit (MSB) is always first. Each byte

has to be followed by an acknowledge bit (see

further below). The number of bytes transmitted per

transfer is unrestricted.

SDA

SCL

Figure 3. I

® bus protocol definitions

Bus communication includes Acknowledge (A) and

not Acknowledge (N) messages. To send an

acknowledge the receiver device pulls the SDA low

for one SCL clock cycle. For not acknowledge (N)

the receiver device leaves the SDA high for one

SCL clock cycle in which case the master can then

generate either a Stop (P) bit to abort the transfer,

or a repeated Start (Sr) bit to start a new transfer.

Abbreviations:

A= Acknowledge by Receiver

N = Not Acknowledge by Receiver

S = Start

Sr = Repeated Start

P = Stop

= from Master (MCU) to Slave (MAS6502)

= from Slave (MAS6502) to Master (MCU)

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