AD9852

–9–

REV. 0

Figures 8–11 show the tradeoff in elevated noise floor, increased phase noise, and occasional discrete spurious energy when the

internal REFCLK Multiplier circuit is engaged. Plots with wide (1 MHz) and narrow (50 kHz) spans are shown.

0

CENTER 39.1MHz

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

100kHz/

SPAN 1MHz

Figure 10. Narrowband SFDR, 39.1 MHz, 1 MHz BW,

30 MHz EXTCLK with REFCLK Multiply = 10

×

0

CENTER 39.1MHz

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

5kHz/

SPAN 50kHz

Figure 11. Narrowband SFDR, 39.1 MHz, 50 kHz BW,

30 MHz EXTCLK/REFCLK Multiplier = 10

×

0

CENTER 39.1MHz

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

5kHz/

SPAN 50kHz

Figure 12. Narrowband SFDR, 39.1 MHz, 50 kHz BW,

100 MHz EXTCLK with REFCLK Multiplier Bypassed

0

CENTER 39.1MHz

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

100kHz/

SPAN 1MHz

Figure 8. Narrowband SFDR, 39.1 MHz, 1 MHz BW,

300 MHz EXTCLK with REFCLK Multiply Bypassed

0

CENTER 39.1MHz

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

5kHz/

SPAN 50kHz

Figure 9. Narrowband SFDR, 39.1 MHz, 50 kHz BW,

300 MHz EXTCLK with REFCLK Multiplier Bypassed

Figures 12 and 13 show the slight increase in noise floor both with and without the PLL when slower clock speeds are used to

generate the same fundamental frequency, that is, with a 100 MHz clock as opposed to a 300 MHz clock in Figures 9 and 11.

0

CENTER 39.1MHz

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

5kHz/

SPAN 50kHz

Figure 13. Narrowband SFDR, 39.1 MHz, 50 kHz BW,

10 MHz EXTCLK with REFCLK Multiplier = 10

×