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AD9852

–27–

REV. 0

Serial Port I/O Operation

With the S/P SELECT pin tied low, the serial I/O mode is

active. The AD9852 serial port is a flexible, synchronous,

serial communications port allowing easy interface to many

industry-standard microcontrollers and microprocessors. The

serial I/O is compatible with most synchronous transfer formats,

including both the Motorola 6905/11 SPI and Intel 8051 SSR

protocols. The interface allows read/write access to all twelve

registers that conﬁgure the AD9852 and can be conﬁgured as a

single pin I/O (SDIO) or two unidirectional pins for in/out (SDIO/

SDO). Data transfers are supported in most signiﬁcant bit (MSB)

ﬁrst format or least signiﬁcant bit (LSB) ﬁrst format at up to

10 MHz.

When conﬁgured for serial I/O operation, most pins from the

AD9852 parallel port are inactive; some are used for the serial

I/O. Table VI describes pin requirements for serial I/O.

Table VI. Serial I/O Pin Requirements

Number

Name

Serial I/O Description

1, 2, 3, 4,

D[7:0]

The parallel data pins are not active, tie

5, 6, 7, 8

to VDD or GND.

14, 15, 16

A[5:3]

The parallel address Pins A5, A4, A3

are not active, tie to VDD or GND.

IORESET

SDO

SDIO

I/O UD

Update Clock. Same functionality for

Serial Mode as Parallel Mode.

WRB

SCLK

RDB

CSB—Chip Select

GENERAL OPERATION OF THE SERIAL INTERFACE

There are two phases to a communication cycle with the AD9852.

Phase 1 is the instruction cycle, which is the writing of an

instruction byte into the AD9852, coincident with the ﬁrst eight

SCLK rising edges. The instruction byte provides the AD9852

serial port controller with information regarding the data transfer

cycle, which is Phase 2 of the communication cycle. The Phase

1 instruction byte deﬁnes whether the upcoming data transfer is

read or write, and the register address in which to transfer data

to/from.

The ﬁrst eight SCLK rising edges of each communication cycle

are used to write the instruction byte into the AD9852. The

remaining SCLK edges are for Phase 2 of the communication

cycle. Phase 2 is the actual data transfer between the AD9852

and the system controller. The number of data bytes transferred

in Phase 2 of the communication cycle is a function of the regis-

ter address. The AD9852 internal serial I/O controller expects

every byte of the register being accessed to be transferred. Table

VII describes how many bytes must be transferred.

Table VII. Register Address vs. Data Bytes Transferred

Serial

Number

of Bytes

Address

Transferred

Phase Offset Tuning Word Register #1

2 Bytes

Phase Offset Tuning Word Register #2

2 Bytes

Frequency Tuning Word #1

6 Bytes

Frequency Tuning Word #2

6 Bytes

Delta Frequency Register

6 Bytes

Update Clock Rate Register

4 Bytes

Ramp Rate Clock Register

3 Bytes

Control Register

4 bytes

I Path Digital Multiplier Register

2 Bytes

Q Path Digital Multiplier Register

2 Bytes

Shaped On/Off Keying Ramp Rate Register

2 Bytes

Q DAC Register

Bytes

At the completion of any communication cycle, the AD9852

serial port controller expects the next eight rising SCLK edges

to be the instruction byte of the next communication cycle. In

addition, an active high input on the IORESET pin immediately

terminates the current communication cycle. After IORESET

returns low, the AD9852 serial port controller requires the next

eight rising SCLK edges to be the instruction byte of the next

communication cycle.

All data input to the AD9852 is registered on the rising edge of

SCLK. All data is driven out of the AD9852 on the falling edge

of SCLK.

Figures 51 and 52 are useful in understanding the general opera-

tion of the AD9852 Serial Port.

INSTRUCTION

CYCLE

DATA TRANSFER

INSTRUCTION

BYTE

DATA BYTE 1

DATA BYTE 2

DATA BYTE 3

SDIO

Figure 51. Using SDIO as a Read/

Write Transfer

INSTRUCTION

CYCLE

DATA TRANSFER

INSTRUCTION

BYTE

SDIO

DATA TRANSFER

DATA BYTE 1

DATA BYTE 2

DATA BYTE 3

SDO

Figure 52. Using SDIO as an Input, SDO as an Output

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