AD9852ASQ datasheet(35/42 Pages) AD

35 / 42 page

AD9852

–35–

REV. 0

and complementary output paths of the sine DAC to remove

images and aliased harmonics and other spurious signals above

approximately 120 MHz. These signals will appear as nearly pure

sine waves and exactly 180 degrees out-of-phase with each other.

Again, if the system clock utilized is much less than 300 MHz, for

example, 200 MHz, unwanted DAC products other than the

fundamental signal will be passed by the low-pass ﬁlters.

1. Install shorting jumpers at W7 and W10.

2. Install shorting jumper at W16.

3. Install shorting jumper on Pins 2 and 3 (top two pins) of 3-

pin header W1.

4. Install shorting jumper on Pins 2 and 3 (top two pins) of 3-

pin header W4.

5. Install shorting jumper on Pins 1 and 2 (top two pins) of 3-

pin header W2 and W8.

Connecting the High-Speed Comparator in a Single-Ended

Conﬁguration

This will allow duty cycle or pulsewidth control and requires

that a dc threshold voltage be present at one of the comparator

inputs. You may supply this voltage using the control DAC. A

12-bit, twos-complement value is written to the control DAC

Allowable hexadecimal values are 7FF (maximum) to 800

(minimum) with all 0s being midscale. The IOUT1 channel will

continue to output a ﬁltered sine wave programmed by the user.

These two signals are routed to the comparator inputs using

W2 and W8 3-pin header switches. The conﬁguration described

above entitled “Observing the Filtered IOUT1 and the Filtered

IOUT2” must be used. Follow steps 1 through 4 above and

then the following Step 5.

5. Install shorting jumper on Pins 2 and 3 (bottom two pins) of

3-pin header W2 and W8

User should elect to change the RSET resistor from 3900

Ω to

1950

Ω to obtain a more robust signal at the comparator inputs.

This will decrease jitter and extend comparator operating range.

User can accomplish this by soldering a second 3.9 k

Ω chip

resistor in parallel with the provided R2.

USING THE CONTROL SOFTWARE

The control software for the AD9852/PCB evaluation board is

provided on a CD. This brief set of instructions should be used

in conjunction with the AD9852/PCB evaluation board schematic.

Several numerical entries, such as frequency and phase infor-

mation, require that the ENTER key by pressed to register

that information.

1. Select the proper printer port. Click the “Parallel Port”

selection in the menu bar. Select the port that matches your

PC. If unknown, experiment by performing the following on

the selected port. With the part powered up, properly clocked

and connected to the PC, select a port and go to the “Mode

and Frequency” menu and click the “Reset DUT and Initialize

Registers” button. Then go to the “Clock and Amplitude”

menu. Once there, click the box next to “Bypass Inverse Sinc

Filter” . . . a check mark will appear in the box . . . next click

the button “Send Control Info to DUT.” If the proper port

has been selected, the supply current going to the AD9852/

PCB evaluation board should drop by approximately 1/3 when

the inverse sinc ﬁlters are bypassed. Conversely, the supply

current will increase approximately 1/3 when the inverse sinc

ﬁlters are engaged.

2. Normal operation of the AD9852/PCB evaluation board

begins with a master reset. Many of the default register values

after reset are depicted in the software “control panel.” The

reset command sets the DDS output amplitude to minimum

and 0 Hz, 0 phase-offset as well as other states listed in the

AD9852 Register Layout table in the preliminary data sheet.

3. The next programming block should be the “Reference Clock

and Multiplier” since this information is used to determine

the proper 48-bit frequency tuning words that will be entered

and calculated later.

4. The output amplitude defaults to the 12-bit straight binary

multiplier values of the I and Q multiplier registers of 000hex

and no output should be seen from the DACs. User should

now set both multiplier amplitudes in the Output Amplitude

window to a substantial value, such as FFFhex. You may

bypass the digital multiplier by clicking the box “Output

Amplitude is always Full-Scale” but experience has shown

that doing so does not result in best SFDR It is interesting

to note that best SFDR, as much as 11 dB better, is obtained

by routing the signal through the digital multiplier and “backing

off” on the multiplier amplitude. For instance, FC0 hex

produces less spurious signal amplitude than FFF hex. Its a

repeatable phenomenon that should be investigated exploited

for maximum SFDR (spurious-free dynamic range).

5. Refer to this data sheet and evaluation board schematic to

understand all the functions of the AD9852 available to the

user and to gain an understanding of what the software is

doing in response to programming commands.

Applications assistance is available for the AD9852, the

AD9852/PCB evaluation board, and all other Analog Devices

products. Please call 1/800-ANALOGD.

AD9852ASQ 数据表(PDF) 35 Page - Analog Devices

AD9852ASQ 数据表(HTML) 35 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

数据表下载