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AD9852ASQ 数据表(PDF) 2 Page - Analog Devices |
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AD9852ASQ 数据表(HTML) 2 Page - Analog Devices |
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2 / 42 page  –2– REV. 0 AD9852–SPECIFICATIONS (V S = 3.3 V 5%, RSET = 3.9 k external reference clock frequency = 30 MHz with REFCLK Multiplier enabled at 10 for AD9852ASQ, external reference clock frequency = 20 MHz with REFCLK Multiplier enabled at 10 for AD9852AST, unless otherwise noted.) Test AD9852ASQ AD9852AST Parameter Temp Level Min Typ Max Min Typ Max Unit REF CLOCK INPUT CHARACTERISTICS1 Internal Clock Frequency Range FULL VI 5 300 5 200 MHz External REF Clock Frequency Range REFCLK Multiplier Enabled FULL VI 5 75 5 50 MHz REFCLK Multiplier Disabled FULL VI 5 300 5 200 MHz Duty Cycle 25 °C V 50 50 % Input Capacitance 25 °CIV 3 3 pF Input Impedance 25 °C IV 100 100 k Ω Differential Mode Common-Mode Voltage Range Minimum Signal Amplitude 25 °C IV 800 800 mV p-p Common-Mode Range 25 °C IV 1.6 1.75 1.9 1.6 1.75 1.9 V VIH (Single-Ended Mode) 25 °C IV 2.3 2.3 V VIL (Single-Ended Mode) 25 °CIV 1 1 V DAC STATIC OUTPUT CHARACTERISTICS Output Update Speed FULL I 300 200 MSPS Resolution 25 °C IV 12 12 Bits Sine and Aux. DAC Full-Scale Output Current 25 °C IV 5 10 20 5 10 20 mA Gain Error 25 °C I –6 +2.25 –6 +2.25 % FS Output Offset 25 °CI 2 2 µA Differential Nonlinearity 25 °C I 0.3 1.25 0.3 1.25 LSB Integral Nonlinearity 25 °C I 0.6 1.66 1 1.66 LSB Output Impedance 25 °C I 100 100 k Ω Voltage Compliance Range 25 °C I –0.5 +1.0 –0.5 +1.0 V DAC WIDEBAND SFDR 1 MHz to 20 MHz AOUT 25 °C V 58 58 dBc 20 MHz to 40 MHz AOUT 25 °C V 56 56 dBc 40 MHz to 60 MHz AOUT 25 °C V 52 52 dBc 60 MHz to 80 MHz AOUT 25 °C V 48 48 dBc 80 MHz to 100 MHz AOUT 25 °C V 48 48 dBc 100 MHz to 120 MHz AOUT 25 °C V 50 dBc DAC NARROWBAND SFDR 10 MHz AOUT (± 1 MHz) 25 °C V 83 83 dBc 10 MHz AOUT (± 250 kHz) 25 °C V 83 83 dBc 10 MHz AOUT (± 50 kHz) 25 °C V 91 91 dBc 41 MHz AOUT (± 1 MHz) 25 °C V 82 82 dBc 41 MHz AOUT (± 250 kHz) 25 °C V 84 84 dBc 41 MHz AOUT (± 50 kHz) 25 °C V 89 89 dBc 119 MHz AOUT (± 1 MHz) 25 °C V 71 71 dBc 119 MHz AOUT (± 250 kHz) 25 °C V 77 77 dBc 119 MHz AOUT (± 50 kHz) 25 °C V 83 83 dBc RESIDUAL PHASE NOISE (AOUT = 5 MHz, Ext. CLK = 30 MHz, REFCLK Multiplier Engaged at 10 ×) 1 kHz Offset 25 °C V 140 140 dBc/Hz 10 kHz Offset 25 °C V 138 138 dBc/Hz 100 kHz Offset 25 °C V 142 142 dBc/Hz (AOUT = 5 MHz, Ext. CLK = 300 MHz, REFCLK Multiplier Bypassed) 1 kHz Offset 25 °C V 142 142 dBc/Hz 10 kHz Offset 25 °C V 148 148 dBc/Hz 100 kHz Offset 25 °C V 152 152 dBc/Hz PIPELINE DELAYS Phase Accumulator and DDS Core 25 °C IV 17 17 SysClk Cycles Inverse Sinc Filter 25 °C IV 12 12 SysClk Cycles Digital Multiplier 25 °C IV 10 10 SysClk Cycles |
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