 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
AD9852ASQ 数据表(PDF) 3 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9852ASQ 数据表(HTML) 3 Page - Analog Devices |
|
|
3 / 42 page  –3– REV. 0 AD9852 Test AD9852ASQ AD9852AST Parameter Temp Level Min Typ Max Min Typ Max Unit MASTER RESET DURATION 25 °C IV 10 10 SysClk Cycles COMPARATOR INPUT CHARACTERISTICS Input Capacitance 25 °CV 3 3 pF Input Resistance 25 °C IV 500 500 ±1kΩ Input Current 25 °CI ±1 ±5 ±1 ±5 µA Hysteresis 25 °C IV 10 20 10 20 mV p-p COMPARATOR OUTPUT CHARACTERISTICS Logic “1” Voltage, High Z Load FULL VI 3.10 3.10 V Logic “0” Voltage, High Z Load FULL VI 0.16 0.16 V Output Power, 50 Ω Load, 120 MHz Toggle Rate 25°C I 9 11 9 11 dBm Propagation Delay 25 °CIV 3 3 ns Output Duty Cycle Error2 25 °CI –10 ±1 +10 –10 ±1 +10 % Rise/Fall Time, 5 pF Load 25 °CV 2 2 ns Toggle Rate, High Z Load 25 °C IV 300 350 300 350 MHz Toggle Rate, 50 Ω Load 25 °C IV 375 400 375 400 MHz Output Cycle-to-Cycle Jitter3 25 °C IV 3 3 ps rms COMPARATOR NARROWBAND SFDR4 10 MHz ( ±1 MHz) 25 °C V 84 84 dBc 10 MHz ( ±250 kHz) 25 °C V 84 84 dBc 10 MHz ( ±50 kHz) 25 °C V 92 92 dBc 41 MHz ( ±1 MHz) 25 °C V 76 76 dBc 41 MHz ( ±250 kHz) 25 °C V 82 82 dBc 41 MHz ( ±50 kHz) 25 °C V 89 89 dBc 119 MHz ( ±1 MHz) 25 °C V 73 73 dBc 119 MHz ( ± 250 kHz) 25 °C V 73 73 dBc 119 MHz ( ± 50 kHz) 25 °C V 83 83 dBc CLOCK GENERATOR OUTPUT JITTER4 5 MHz AOUT 25 °C V 23 23 ps rms 40 MHz AOUT 25 °C V 12 12 ps rms 100 MHz AOUT 25 °C V 7 7 ps rms PARALLEL I/O TIMING CHARACTERISTICS TASU (Address Setup Time to WR Signal Active) FULL IV 4 4 ns TADHW (Address Hold Time to WR Signal Inactive) FULL IV 3 3 ns TDSU (Data Setup Time to WR Signal Inactive) FULL IV 2 2 ns TDHD (Data Hold Time to WR Signal Inactive) FULL IV 0 0 ns TWRLOW (WR Signal Minimum Low Time) FULL IV 3 3 ns TWRHIGH (WR Signal Minimum High Time) FULL IV 7 7 ns TWR (WR Signal Minimum Period) FULL IV 10 10 ns TADV (Address to Data Valid Time) FULL V 15 15 15 15 ns TADHR (Address Hold Time to RD Signal Inactive) FULL IV 5 5 ns TRDLOV (RD Low-to-Output Valid) FULL IV 15 15 ns TRDHOZ (RD High-to-Data Three-State) FULL IV 10 10 ns SERIAL I/O TIMING CHARACTERISTICS TPRE (CS Setup Time) FULL IV 30 30 ns TSCLK (Period of Serial Data Clock) FULL IV 100 100 ns TDSU (Serial Data Setup Time) FULL IV 30 30 ns TSCLKPWH (Serial Data Clock Pulsewidth High) FULL IV 40 40 ns TSCLKPWL (Serial Data Clock Pulsewidth Low) FULL IV 40 40 ns TDHLD (Serial Data Hold Time) FULL IV 0 0 ns TDV (Data Valid Time) FULL V 30 30 ns CMOS LOGIC INPUTS Logic “1” Voltage 25 °C I 2.7 2.7 V Logic “0” Voltage 25 °C I 0.4 0.4 V Logic “1” Current 25 °CIV ±5 ±5 µA Logic “0” Current 25 °CIV ±5 ±5 µA Input Capacitance 25 °CV 3 3 pF |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
