AD9852ASQ datasheet(13/42 Pages) AD

13 / 42 page

AD9852

–13–

REV. 0

TUNING

WORD

VCO

LOOP

FILTER

PHASE

COMPARATOR

REF

CLOCK

FREQUENCY

OUT

FILTER

AD9852

DDS

DIVIDE-BY-N

Figure 28. Agile High-Frequency Synthesizer

PROCESSOR/

CONTROLLER

FPGA, ETC.

RSET

8-BIT PARALLEL OR

SERIAL PROGRAMMING

DATA AND CONTROL

SIGNALS

AD9852

CMOS LOGIC "CLOCK" OUT

REFERENCE

CLOCK

300MHz MAX DIRECT

MODE OR 15 TO 75MHz

MAX IN THE 4 -20

CLOCK

MULTIPLIER MODE

CONTROL

"I" DAC

NOTES:

IOUT = APPROX 20mA MAX WHEN RSET = 2k

SWITCH POSTION 1 PROVIDES COMPLEMENTARY SINUSOIDAL SIGNALS TO THE COMPARATOR

TO PRODUCE A FIXED 50% OUTPUT DUTY CYCLE FROM THE COMPARATOR.

SWITCH POSTION 2 PROVIDES A USER PROGRAMMABLE DC THRESHOLD VOLTAGE TO ALLOW

SETTING OF THE COMPARATOR OUTPUT DUTY CYCLE.

LOW-PASS

FILTER

LOW-PASS

FILTER

Figure 30. Frequency Agile Clock Generator Applications for the AD9852

(continued from page 1)

generation of a sine output at frequencies up to 150 MHz, which

can be digitally tuned at a rate of up to 100 million new frequencies

per second. The (externally ﬁltered) sine wave output can be

converted to a square wave by the internal comparator for agile

clock generator applications. The device provides 14 bits of

digitally-controlled phase modulation and single-pin PSK. The

on-board 12-bit DAC, coupled with the innovative DDS

architecture, provide excellent wideband and narrowband out-

put SFDR. There is also an auxiliary DAC that can be conﬁgured

as a user-programmable control DAC. When conﬁgured with

the on-board comparator, the 12-bit control DAC facilitates

duty cycle control, in the high-speed clock generator application. A

12-bit digital multiplier permits programmable amplitude modu-

lation, shaped on/off keying and precise amplitude control of

the output. Chirp functionality is also included which facilitates

wide bandwidth frequency sweeping applications. The AD9852’s

programmable 4

×–20× REFCLK multiplier circuit generates

the 300 MHz clock internally from a lower frequency external

reference clock. This saves the user the expense and difﬁculty of

implementing a 300 MHz clock source. Direct 300 MHz clocking

is also accommodated with either single-ended or differential

inputs. Single-pin conventional FSK and the enhanced spectral

qualities of “ramped” FSK are supported. The AD9852 uses

advanced 0.35 micron CMOS technology to provide this high

level of functionality on a single 3.3 V supply.

The AD9852 is available in a space-saving 80-lead LQFP

surface-mount package and a thermally-enhanced 80-lead LQFP

package. The AD9852 is pin-for-pin compatible with the AD9854

quadrature output synthesizer device. It is speciﬁed to operate over

the extended industrial temperature range of –40

°C to +85°C.

OVERVIEW

The AD9852 digital synthesizer is a highly flexible device that

will address a wide range of applications. The device consists

of an NCO with 48-bit phase accumulator, programmable ref-

erence clock multiplier, inverse sinc ﬁlters, digital multipliers,

two 12-bit/300 MHz DACs, high-speed analog comparator,

and interface logic. This highly integrated device can be conﬁg-

ured to serve as a synthesized L.O., agile clock generator, and

FSK/BPSK modulator. The theory of operation of the func-

tional blocks of the device, and a technical description of the

signal flow through a DDS device, can be found in a tutorial

from Analog Devices, called, “A Technical Tutorial on Digital

Signal Synthesis.” This tutorial is available on CD-ROM and

information on obtaining it can be found at the Analog Devices

DDS website at www.analog.com/dds. The tutorial also

provides basic applications information for a variety of digital

synthesis implementations. The DDS background subject matter is

not covered in this data sheet; the functions and features of

the AD9852 will be individually discussed herein.

REFERENCE

CLOCK

1:1 TRANSFORMER

I.E. MINI-CIRCUITS T1–1T

FILTER

DIFFERENTIAL

TRANSFORMER-COUPLED

OUTPUT

AD9852

DDS

IOUT

Figure 29. Differential Output Connection for Reduction of

Common-Mode Signals

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