AD9856

–4–

REV. B

Pin #

Pin Name

Pin Function

1

TxENABLE

Input Pulse that Synchronizes

the Data Stream

2

D11

Input Data (Most Significant Bit)

3

D10

Input Data

4, 10,

21, 44

DVDD

Digital Supply Voltage

5, 11,

20, 43

DGND

Digital Ground

6–9

D9–D6

Input Data

12–16

D5–D1

Input Data

17

D0

Input Data (Least Significant

Bit)

18, 19,

22

NC

No Internal Connection

23, 28,

31

AGND

Analog Ground

24

BG REF BYPASS

No External Connection*

25

26

DAC REF BYPASS

No External Connection*

27

AVDD

Analog Supply Voltage

Pin #

Pin Name

Pin Function

29

Complementary Analog

Current Output of the DAC

30

True Analog Current Output

of DAC

32

PLL GND

PLL Ground

33

PLL FILTER

PLL Loop Filter Connection

34

PLL SUPPLY

PLL Voltage Supply

35

CA ENABLE

Cable Driver Amp Enable

36

CA DATA

Cable Driver Amp Data

37

CA CLK

Cable Driver Amp Clock

38

CS

Chip Select

39

SDO

Serial Data Output

40

SDIO

Serial Port I/O

41

SCLK

Serial Port Clock

42

SYNC I/O

Performs I/O Synchronization

45

PS0

Profile Select 0

46

PS1

Profile Select 1

47

REFCLK

Reference Clock Input

48

RESET

Master Reset

PIN FUNCTION DESCRIPTIONS

PIN CONFIGURATION

36

35

34

33

32

31

30

29

28

27

26

25

13 14 15 16 17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

48 47 46 45 44

39 38

43 42 41 40

37

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

AD9856

CA DATA

CA ENABLE

PLL SUPPLY

PLL FILTER

PLL GND

AGND

TxENABLE

D11

D10

DVDD

DGND

D9

D8

NC = NO CONNECT

D7

D6

DVDD

DGND

AGND

AVDD

DAC REF BYPASS

D5

*In most cases optimal performance is achieved with no external connection. For extremely noisy environments BG REF BYPASS can be bypassed with up to a

0.1

µF capacitor to AGND (Pin 23). DAC REF BYPASS can be bypassed with up to a 0.1 µF capacitor to AVDD (Pin 27).