AD9856SLASHPCB datasheet(16/32 Pages) AD

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AD9856

–16–

REV. B

TxENABLE

D(11:0)

INTERNAL I

INTERNAL Q

IN–2

IN–1

QN–2

QN–1

LOGIC 0

Figure 26. Burst Mode Input Timing—End of Burst

IN+1

QN+1

IN+2

QN+2

IN+3

QN+3

IN+4

QN+4

IN+5

IN+1

IN+2

IN+3

TxENABLE

D(11:0)

INTERNAL I

INTERNAL Q

IN–1

QN–1

QN+4

IN+4

QN+3

Figure 27. Continuous Mode Input Timing—TxENABLE Static High

IN+1

QN+1

IN+2

QN+2

IN+3

QN+3

IN+4

QN+4

QN+2

QN+1

IN+3

TxENABLE

D(11:0)

INTERNAL I

INTERNAL Q

IN–1

QN–1

QN+3

Figure 28. Continuous Mode Input Timing—TxENABLE Static Low

Figure 26 describes the end of burst timing and internal data

assembly. It’s important to note that in burst mode operation, if

the TxENABLE input is low for more than one input sample

period, numerical zeros are internally generated and passed to

the data path logic for signal processing. This is not valid for

continuous mode operation, as will be discussed later.

To ensure proper operation, the minimum time between falling

and rising edges of TxENABLE is one input sample period.

Continuous Mode Input Timing

The AD9856 is configured for continuous mode input timing by

writing the Continuous Mode bit true (Logic 1). The Continu-

ous Mode bit is in register address 01h, Bit 6. The AD9856

must be configured for full word input format when operating in

continuous mode input timing. The input data rate equations

described above, for full word mode, apply for continuous mode.

Figure 23, which is the alternate burst mode timing diagram, is

also the continuous mode input timing. Figures 27 and 28 de-

scribe what the internal data assembler will present to the signal

processing logic when the TxENABLE input is held static for

greater than one input sample period. Please note that the tim-

ing diagram of Figures 27 and 28 detail INCORRECT timing

relationships between TxENABLE and data. They are only

presented to indicate that the AD9856 will resynchronize

properly after detecting a rising edge of TxENABLE. It should

also be noted that the significant difference between burst and

continuous mode operation is that in addition to synchronizing

the data, TxENABLE is used to indicate whether an I or Q

input is being sampled.

Do not engage continuous mode simultaneously with the

REFCLK multiplier function. This has been found to corrupt

the CIC interpolating filter, forcing unrecoverable mathematical

overflow that can only be resolved by issuing a RESET com-

mand. The problem is due to the PLL failing to be locked to the

reference clock while nonzero data is being clocked into the

interpolation stages from the data inputs. The recommended

sequency is to first engage the REFCLK multiplier function

(allowing at least 1 ms for loop stabilization) and then engage

continuous mode via software.

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