AD9856SLASHPCB datasheet(22/32 Pages) AD

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AD9856

–22–

REV. B

INVERSE SINC FILTER (ISF)

The AD9856 is almost entirely a digital device. The input

“signal” is made up of a time series of digital data words. These

data words propagate through the device as numbers. Ultimately,

this number stream must be converted to an analog signal. To

this end, the AD9856 incorporates an integrated DAC. The

output waveform of the DAC is the familiar “staircase” pattern

typical of a signal that is sampled and quantized. The staircase

pattern is a result of the finite time that the DAC holds a quan-

tized level until the next sampling instant. This is known as a

zero-order hold function. The spectrum of the zero-order hold

function is the familiar SIN(x)/x, or SINC, envelope.

The series of digital data words presented at the input of the

DAC represent an impulse stream. It is the spectrum of this

impulse stream, which is the desired output signal. Due to the

zero-order hold effect of the DAC, however, the output spec-

trum is the product of the zero-order hold spectrum (the SINC

envelope) and the Fourier transform of the impulse stream.

Thus, there is an intrinsic distortion in the output spectrum,

which follows the SINC response.

The SINC response is deterministic and totally predictable.

Thus, it is possible to pre-distort the input data stream in a

manner, which compensates for the SINC envelope distortion.

This can be accomplished by means of an ISF. The ISF incor-

porated on the AD9856 is a 17-tap, linear phase FIR filter. Its

frequency response characteristic is the inverse of the SINC

envelope. Data sent through the ISF is altered in such a way as

to correct for the SINC envelope distortion.

It should be noted, however, that the ISF is sampled at the

same rate as the DAC. Thus, the effective range of the SINC

envelope compensation only extends to the Nyquist frequency

(1/2 of the DAC sample rate).

Figure 33 is a plot that shows the effectiveness of the ISF in

correcting for the SINC distortion. The plot includes a graph of

the SINC envelope, the ISF response and the SYSTEM re-

sponse (which is the product of the SINC and ISF responses).

It should be mentioned at this point that the ISF exhibits an

insertion loss of 3.1 dB. Thus, signal levels at the output of the

AD9856 with the ISF bypassed are 3.1 dB higher than with the

ISF engaged. However, for modulated output signals, which

have a relatively wide bandwidth, the benefits of the SINC

FREQUENCY NORMALIZED TO SAMPLE RATE

–0.5

–4.0

0.1

0.2

0.3

0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

1.5

1.0

0.5

0.4

2.0

4.0

3.5

3.0

2.5

ISF

SINC

SYSTEM

Figure 33. Inverse SINC Filter Response

compensation usually outweigh the 3 dB loss in output level.

The decision of whether or not to use the ISF is an application

specific system design issue.

DIRECT DIGITAL SYNTHESIZER FUNCTION

The direct digital synthesizer (DDS) block generates the sine/

cosine carrier reference signals that are digitally modulated by

the I/Q data paths. The DDS function is frequency tuned via

the serial control port with a 32-bit tuning word. This allows the

AD9856’s output carrier frequency to be very precisely tuned

while still providing output frequency agility.

The equation relating output frequency of the AD9856 digital

modulator to the frequency tuning word (FTWORD) and the

system clock (SYSCLK) is given as:

AOUT = (FTWORD × SYSCLK)/2

Where: AOUT and SYSCLK frequencies are in Hz and

FTWORD is a decimal number from 0 to 4,294,967,296 (2

31)

Example: Find the FTWORD for AOUT = 41 MHz and

SYSCLK = 122.88 MHz

If AOUT = 41 MHz and SYSCLK = 122.88 MHz, then:

FTWORD = 556AAAAB hex

Loading 556AAAABh into control bus registers 02h–05h (for

Profile 1) programs the AD9856 for AOUT = 41 MHz, given a

SYSCLK frequency of 122.88 MHz.

D/A CONVERTER

A 12-bit digital-to-analog converter (DAC) is used to convert

the digitally processed waveform into an analog signal. The

worst case spurious signals due to the DAC are the harmonics of

the fundamental signal and their aliases (please see the AD9851

Complete-DDS data sheet for a detailed explanation of aliased

images). The wideband 12-bit DAC in the AD9856 maintains

spurious-free dynamic range (SFDR) performance of –60 dBc

up to AOUT = 42 MHz and –55 dBc up to AOUT = 65 MHz.

The conversion process will produce aliased components of the

fundamental signal at n

× SYSCLK ± F

CARRIER (n = 1, 2, 3).

These are typically filtered with an external RLC filter at the

DAC output. It is important for this analog filter to have a suffi-

ciently flat gain and linear phase response across the bandwidth

of interest so as to avoid modulation impairments. A relatively

inexpensive 7th order elliptical low-pass filter is sufficient to

suppress the aliased components for HFC network applications.

The AD9856 provides true and complement current outputs on

pins 30 and 29 respectively. The full-scale output current is set

by the RSET resistor at Pin 25. The value of RSET for a particular

IOUT is determined using the following equation:

RSET = 39.936/IOUT

For example, if a full-scale output current of 20 mA is desired,

then RSET = (39.936/0.02), or approximately 2 k

Ω. Every dou-

bling of the RSET value will halve the output current. Maximum

output current is specified as 20 mA.

The full-scale output current range of the AD9856 is 5 mA–

20 mA. Full-scale output currents outside of this range will

degrade SFDR performance. SFDR is also slightly affected by

output matching, that is, the two outputs should be terminated

equally for best SFDR performance.

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