AD9856SLASHPCB datasheet(28/32 Pages) AD

28 / 32 page

AD9856

–28–

REV. B

POWER DISSIPATION CONSIDERATIONS

The majority of the AD9856 power dissipation comes from

digital switching currents. As such, power dissipation is highly

dependent upon chip configuration.

Obviously, the major contributor to switching current is the

maximum clock rate at which the device is operated, but other

factors can play a significant role. Factors such as the CIC inter-

polation rate, and whether the third half-band filter and inverse

SINC filters are active, can affect the power dissipation of the

device.

It is important for the user to consider all of these factors when

optimizing performance for power dissipation. For example,

there are two ways to achieve a 6 MS/s transmission rate with

the AD9856. The first method uses an fMAX of 192 MHz; the

other method uses an fMAX of 144 MHz, which reduces power

dissipation by nearly 25%.

For the first method, the input data must be externally 4

× up-

sampled. The AD9856 must be configured for a CIC interpola-

tion rate of three while bypassing the 3rd half-band filter. This

results in an I/Q input sample rate of 24 MHz which is further

upsampled by a factor of 8 to 192 MHz.

The second method requires an fMAX of 144 MHz with exter-

nally 2

× upsampled input data. The AD9856 is configured for

a CIC interpolation rate of 3 while bypassing the 3rd half-band

filter. The input I/Q sample rate is 12 MHz, which is further

upsampled by a factor of 12 MHz to 144 MHz.

For burst applications with relatively long nonbursting periods,

the sleep bit is useful for saving power. When in sleep mode,

power is reduced to below 6 mW. Consideration must be given

to wake-up time, which will generally be in the 400

µs to 750 µs

range. For those applications that cannot use the sleep bit due

to this wake-up time, there is an alternate method of reducing

power dissipation when not transmitting. By writing the “Bypass

REFCLK Multiplier” bit active, the power is reduced by nearly

the REFCLK Multiplier factor. For example, if the external

reference clock is 16 MHz and REFCLK Multiplier is set to

×, all clocks will divide down by a factor of 10 when the

REFCLK Multiplier is bypassed. This effectively scales down

the power dissipation by nearly a factor of 10. In this case, both

the REFCLK Multiplier function and the DAC, which use

relatively little power, remain fully powered. The REFCLK

Multiplier circuit is locked to the 16 MHz external reference

clock but its output is driving a very small load, hence very

little power dissipation. When the REFCLK Multiplier is reacti-

vated, the acquisition time is small. In this power-reduction

technique, the larger the REFCLK Multiplier factor, the larger

the power savings.

The AD9856 is specified for operation at +3.0 V

± 5% and the

thermal impedance of the AD9856 in the 48-LQFP plastic

package is 38

°C/W. At 200 MHz operation, power dissipation is

1.5 W. This permits operation over the industrial temperature

range without exceeding the maximum junction temperature of

150

°C. To realize this quoted thermal impedance, all power and

ground pins must be soldered down to a multilayer PCB with

power and ground copper planes directly available at the pack-

age pins.

Under worst case conditions, that is, with power supplies at

+2.85 V and ambient temperatures of +85

°C, device operation

at 200 MHz is guaranteed for single tone mode only. For modu-

lation mode at 200 MHz, +85

°C operation, the minimum power

supply voltage is +3.0 V.

AD9856 EVALUATION BOARD

An evaluation board is available for the AD9856 quadrature

digital upconverter that facilitates bench and system analysis

of the device. The AD9856/PCB contains the AD9856 device

and Windows software that allows control of the device via the

printer port of a PC. The DAC output is provided on a jack for

spectral analysis. The AD9856/PCB circuit board provides a

single-ended 65 MHz, 50

Ω, elliptical low-pass filter on the out-

put of the DAC.

There is also a provision for the user to implement the AD8320/

AD8321 programmable cable driver amplifier on the AD9856/

PCB evaluation board. The AD8320/AD8321 gain is programmed

through the AD9856 via the menu driven control software.

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