AD9856SLASHPCB datasheet(24/32 Pages) AD

24 / 32 page

AD9856

–24–

REV. B

SDIO

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

Figure 34. Serial Port Writing Timing—Clock Stall Low

DO 7

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

DON'T CARE

SDIO

SCLK

SDO

DO 6 DO 5 DO 4 DO 3 DO 2 DO 1

DO 0

Figure 35. Three-Wire Serial Port Read Timing—Clock Stall Low

SDIO

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

Figure 36. Serial Port Write Timing—Clock Stall High

SDIO

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

Figure 37. Two-Wire Serial Port Read Timing—Clock Stall High

At the completion of any communication cycle, the AD9856

serial port controller expects the next 8 rising SCLK edges to be

the instruction byte of the next communication cycle.

All data input to the AD9856 is registered on the rising edge of

SCLK. All data is driven out of the AD9856 on the falling edge

of SCLK.

Figures 34–37 are useful in understanding the general operation

of the AD9856 Serial Port.

INSTRUCTION BYTE

The instruction byte contains the following information as shown

below (see Table III):

Table III. Instruction Byte Information

MSB

LSB

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