AD9856SLASHPCB datasheet(20/32 Pages) AD

20 / 32 page

AD9856

–20–

REV. B

Figure 32. CIC Filter Frequency Response (HB 3 Selected and R = 2, 63)

DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW

–150

1012 1416 18 20

–140

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

22 24 26 28 30 32

a. CIC Frequency Response (R = 2, HBF 3 Selected)

DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW

576

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–140

–150

144 216 288 360 432 504

648 720 792 864 936 1008

b. CIC Frequency Response (R = 63, HBF 3 Active)

DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW

0.2

0.4

0.6

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

0.8

1.0

1.2

1.4

1.6

1.8

2.0

c. Passband Detail (R = 2, HBF 3 Selected)

DISPLAYED FREQUENCY IS RELATIVE TO I/Q NYQ. BW

0.2

0.4

0.6

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

0.8

1.0

1.2

1.4

1.6

1.8

2.0

d. Passband Detail (R = 63, HBF 3 Active)

DIGITAL QUADRATURE MODULATOR

Following the CIC filter stage the I and Q data (which have

been processed independently up to this point) are mixed in the

modulator stage to produce a digital modulated carrier. The

carrier frequency is selected by programming the direct digital

synthesizer (see the DDS section) with the appropriate 32-bit

tuning word via the AD9856 control registers. The DDS simul-

taneously generates a digital (sampled) sine and cosine wave at

the programmed carrier frequency. The digital sine and cosine

data is multiplied by the Q and I data, respectively, to create the

quadrature components of the original data upconverted to the

carrier frequency. The quadrature components are digitally

summed and passed on to the subsequent stages.

The key point is that the modulation is done digitally, which

eliminates the phase and gain imbalance and crosstalk issues

typically associated with analog modulators. Note that the

modulated “signal” is actually a number stream sampled at the

rate of SYSCLK, which is the same rate at which the DAC is

clocked (see Figure 21, the AD9856 block diagram).

It should be pointed out that the architecture of the quadrature

modulator results in a 3 dB loss of signal level. To visualize this,

assume that both the I data and Q data are fixed at the maxi-

mum possible digital value, x. Then the output of the modula-

tor, y, is:

y = x

× cos(ω) + x × sin(ω) = x × [cos(ω) + sin(ω)]

From this equation it can be shown that y assumes a maximum

value of x

√2 (a gain of 3 dB). However, if the same number of

bits were used to represent the y values, as is used to represent

the x values, an overflow would occur. To prevent this possibil-

ity, an effective “divide-by-two” is implemented on the y values,

which reduces the maximum value of y by a factor of two. Since

division by two results in a 6 dB loss, the modulator yields an

overall loss of 3 dB (3 dB – 6 dB = –3 dB, or 3 dB of loss).

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