AD9856SLASHPCB datasheet(27/32 Pages) AD

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AD9856

–27–

REV. B

UNDERSTANDING AND USING PIN SELECTABLE

MODULATOR PROFILES

The AD9856 Quadrature Digital Upconverter is capable of

storing four preconfigured modulation modes called “profiles”

that define the following:

• Output Frequency—32 Bits

• Interpolation Rate—6 Bits

• Spectral Inversion Status—1 Bit

• Bypass 3rd Half-Band Filter—1 Bit

• Gain Control of AD8320/AD8321—8 Bits

Output Frequency: This attribute consists of four 8-bit words

loaded into four register addresses to form a 32-bit frequency

tuning word (FTW) for each profile. The lowest register address

corresponds to the least significant 8-bit word. Ascending

addresses correspond to increasingly significant 8-bit words.

The output frequency equation is given as: fOUT = (FTW

SYSCLK)/2

32.

Interpolation Rate: Consists of a 6-bit word representing the

allowed interpolation values from 2 to 63. Interpolation is the

mechanism used to “up-sample” or multiply the input data rate

such that it exactly matches that of the DDS sample rate

(SYSCLK). This implies that the system clock must be an exact

multiple of the symbol rate. This 6-bit word represents the 6 MSBs

of the eight bits allocated for that address. The remaining two

bits contain the spectral inversion status bit and half-band by-

pass bit.

Spectral Inversion: Single bit that when at Logic 0 the default

or “noninverted” output from the adder is sent to the following

stages. A Logic 1 will cause the inverted output to be sent to the

following stages. The noninverted output is described as I

Cos(

ωt) – Q × Sin(ωt). The inverted output is described as I ×

Cos(

ωt) + Q × Sin(ωt). This bit is located adjacent to the LSB

at the same address as the interpolation rate (see above).

Bypass Third Half-Band Filter: A single bit located in the

LSB position of the same address as the interpolation rate.

When this bit is Logic 0, the third half-band filter is engaged

and its inherent 2

× interpolation rate is applied. When this bit is

Logic 1, the third half-band filter is bypassed and the 2

× inter-

polation rate is negated. This allows users to input higher data

rates—rates that may be too high for the minimum interpolation

rate if all three half-band filters with their inherent 2

× interpola-

tion rate are engaged. The overall effect is to reduce minimum

interpolation rate from 8

× to 4×.

AD8320/AD8321 Gain Control: An 8-bit word that controls

the gain of an AD8320/AD8321 Programmable Gain Amplifier

connected to the AD9856 with the 3-bit SPI interface bus. Gain

range is from –10 dB (00 hex) to +26 dB (FFhex). The gain is

linear in V/V/LSB and follows the equation: AV = 0.316 + 0.077

× Code. Where “Code” is the decimal equivalent of the 8-bit

gain word.

Profile Selection: After profiles have been loaded into the

appropriate registers, the user may select which profile to use

with two input pins: PS0 and PS1, Pins 45 and 46. Profiles are

selected according to the table below.

Table V. Profile Select Matrix

PS1

PS0

PROFILE

Except while in single tone mode, it is recommended that users

suspend the TxENABLE function by bringing that pin to Logic

0 prior to changing from one profile to another and then

reasserting TxENABLE afterwards. This assures that any

dis-continuities resulting from register data transfer are not

transmitted up or downstream. Furthermore, changing interpo-

lation rates during a burst may create an unrecoverable digital

overflow condition that would interrupt transmission of the

current burst until a RESET and reloading procedure would be

completed.

GAIN TRANSFER

CA ENABLE

CA CLK

tDS

CA DATA

VALID DATA WORD G1

MSB...LSB

VALID DATA WORD G2

tWH

tCK

tES

tEH

8 CLOCK CYCLES

SYMBOL

DEFINITION

MIN

tDS

CA DATA SETUP TIME

6.5ns

tDH

CA DATA HOLD TIME

2ns

tWH

CA CLOCK PULSE HIGH

9ns

tCK

CA CLOCK PERIOD

25ns

tES

CA ENABLE SETUP TIME

17ns

tEH

CA ENABLE HOLD TIME

2.0ns

Figure 40. Programmable Cable Driver Amplifier Output Control Interface Timing

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