AD9856SLASHPCB datasheet(14/32 Pages) AD

14 / 32 page

AD9856

–14–

REV. B

Single Tone Output Operation

The AD9856 can be configured for frequency synthesis applica-

tions by writing the single tone bit true. In single tone mode, the

AD9856 disengages the modulator and preceding datapath logic

to output a spectrally pure single frequency sine wave. The

AD9856 provides for a 32-bit frequency tuning word, which

results in a tuning resolution of 0.046 Hz at a SYSCLK rate of

200 MHz.

A good rule of thumb when using the AD9856 as a frequency

synthesizer is to limit the fundamental output frequency to 40%

of SYSCLK. This avoids generating aliases too close to the

desired fundamental output frequency, thus minimizing the cost

of filtering the aliases.

All applicable programming features of the AD9856 apply when

configured in single tone mode. These features include:

1. Frequency hopping via the PROFILE inputs and associated

tuning word, which allows Frequency Shift Keying (FSK)

modulation.

2. Ability to bypass the REFCLK Multiplier, which results in

lower phase noise and reduced output jitter.

3. Ability to bypass the SIN(x)/x compensation filter.

4. Full power-down mode.

INPUT WORD RATE (fW) vs. REFCLK RELATIONSHIP

There is a fundamental relationship between the input word rate

(fW) and the frequency of the clock that serves as the timing

source for the AD9856 (REFCLK). fW is defined as the rate at

which K-bit data words (K = 3, 6 or 12) are presented to the

AD9856. There are, however, a number of factors that affect

this relationship. They are:

• The interpolation rate of the CIC filter stage.

• Whether or not Half-Band Filter #3 is bypassed.

• The value of REFCLK Multiplier (if selected).

• Input Word Length.

This relationship can be summed up with the following equation:

REFCLK = (2 HNfW)/MI

Where H, N, I and M are integers and are determined as follows:

H =

| 1:

Half-Band Filter #3 Bypassed

| 2:

Half-Band Filter #3 Enabled

M =

| 1:

REFCLK Multiplier Bypassed

| 4

≤ M ≤ 20:

REFCLK Multiplier Enabled

| 1:

Full Word Input Format

| 2:

Half Word Input Format

| 4:

Quarter Word Input Format

N =

CIC interpolation rate (2

≤ N ≤ 63)

It should be obvious from these conditions that REFCLK and

fW have an integer ratio relationship. It is of utmost importance

that the user chooses a value of REFCLK, which will ensure

that this integer ratio relationship is maintained.

I/Q DATA SYNCHRONIZATION

As mentioned above, the AD9856 accepts I/Q data pairs, twos

complement numbering system, in three different word length

modes. The full word mode accepts 12-bit parallel I and Q data.

The half word mode accepts dual 6-bit I and Q data inputs to

form a 12-bit word. The quarter word mode accepts multiple

3-bit I and Q data inputs to form a 12-bit word. For all word

length modes, the AD9856 assembles the data for signal pro-

cessing into time aligned, parallel 12-bit I/Q pairs. In addition to

the word length flexibility, the AD9856 operates in two “input

timing” modes, burst or continuous, programmable via the

serial port.

For burst mode input timing, no external data clock needs to be

provided as the data is oversampled at the D<11:0> pins using

the system clock (SYSCLK). The TxENABLE pin is required

to frame the data burst as the rising edge of TxENABLE is used

to synchronize the AD9856 to the input data rate. The AD9856

registers the input data at the approximate center of the data

valid time. It should be obvious that for larger CIC interpola-

tion rates, more SYSCLK cycles are available to oversample

the input data, maximizing clock jitter tolerances.

For continuous mode input timing, the TxENABLE pin can be

thought of as a data input clock running at 1/2 the input sample

rate (fW/2). In addition to synchronization, for continuous mode

timing, the TxENABLE input indicates to the AD9856 whether

an I or Q input is being presented to the D<11:0> pins. It is

intended that data is presented in alternating fashion such that I

data is followed by Q data. Stated another way, the TxENABLE

pin should maintain approximately a 50/50 duty cycle. As in

burst mode, the rising edge of TxENABLE synchronizes the

AD9856 to the input data rate and the data is registered at the

approximate center of the data valid time. The continuous oper-

ating mode can only be used in conjunction with the full word

input format.

Burst Mode Input Timing

Figures 22–26 describe the input timing relationship between

TxENABLE and the 12-bit input data word for all three input

format modes when the AD9856 is configured for burst input

timing. Also shown in these diagrams is the time-aligned, 12-bit

parallel I/Q data as assembled by the AD9856.

Figure 22 describes the classic burst mode timing, for full word

input mode, in which TxENABLE frames the input data stream.

Note that sequential input of alternating I/Q data, starting with

I data, is required.

The input sample rate for full word mode, when the third half-

band filter is engaged, is given by:

fIN = SYSCLK/4N

where N is the CIC interpolation rate.

The input sample rate for full word mode, when the third half-

band filter is not engaged is given by:

fIN = SYSCLK/2N

where N is the CIC interpolation rate

Figure 23 describes an alternate timing method for TxENABLE

when the AD9856 is configured in full word, burst mode

operation. The benefit of this timing is that the AD9856 will

resynchronize the input sampling logic when the rising edge of

TxENABLE is detected. The low time on TxENABLE is lim-

ited to one input sample period and must be low during the Q

data period. The maximum high time on TxENABLE is unlim-

ited. It should be clear that unlimited high time on TxENABLE

results in the timing diagram of Figure 22. See Figure 26 for the

ramifications of violating the TxENABLE low time constraint

when operating in burst mode.

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