REV. A

AD9888

–17–

8 PIPE DELAY

P0

P1

P2

P3

P4

P5

P6

P7

U0

V1

U2

V3

U4

RGBIN

HSYNC

PXCK

HS

ADCCK

DATACK

ROUTA

HSOUT

Y0

Y1

Y2

Y3

Y4

GOUTA

VARIABLE DURATION

Figure 22. 4:2:2 Output Mode

2-WIRE SERIAL REGISTER MAP

The AD9888 is initialized and controlled by a set of registers, which determine the operating modes. An external controller is

employed to write and read the Control Registers through the 2-line serial interface port.

Table V. Control Register Map

Read and

Hex

Write or

Default

Address

Read Only

Bits

Value

Register Name

Function

00H

RO

7:0

Chip Revision

An 8-bit register which represents the silicon revision level. Revision 0

= 0000 0000.

01H

R/

W

7:0

01101001 PLL Div MSB

This register is for Bits [11:4] of the PLL divider. Larger values mean the

PLL operates at a faster rate. This register should be loaded first whenever

a change is needed. (This will give the PLL more time to lock.) See Note

1.

02H

R/

W

7:4

1101

**** PLL Div LSB

Bits [7:4] LSBs of the PLL divider word. See Note 1.

03H

R/

W

7:2

01

****** VCO/CPMP

Bits [7:6] VCO Range. Selects VCO frequency range. (See PLL description.)

**001***

Bits [5:3] Charge Pump Current. Varies the current that drives the low-

pass filter. (See PLL description.)

04H

R/

W

7:3

10000

*** Phase Adjust

ADC Clock phase adjustment. Larger values mean more delay. (1 LSB =

T/32)

05H

R/

W

7:0

00001000 Clamp Placement Places the Clamp signal an integer number of clock periods after the trail-

ing edge of the Hsync signal.

06H

R/

W

7:0

00010100 Clamp Duration

Number of clock periods that the Clamp signal is actively clamping.

07H

R/

W

7:0

00100000 Hsync Output

Sets the number of pixel clocks that HSOUT will remain active.

Pulsewidth

08H

R/

W

7:0

10000000 Red Gain

Controls ADC input range (Contrast) of each respective channel. Bigger

values give less contrast.

09H

R/

W

7:0

10000000 Green Gain

0AH

R/

W

7:0

10000000 Blue Gain

0BH

R/

W

7:1

1000000

* Red Offset

Controls dc offset (Brightness) of each respective channel. Bigger values

decrease brightness.

0CH

R/

W

7:1

1000000

* Green Offset

0DH

R/

W

7:1

1000000

* Blue Offset