AD9888SLASHPCB datasheet(23/32 Pages) AD

23 / 32 page

REV. A

AD9888

–23–

COAST Input Polarity

A bit to indicate the polarity of the COAST signal that is

applied to the PLL COAST input.

Table XX. COAST Input Polarity Settings

CSTPOL

Function

Active LOW

Active HIGH

Active LOW means that the clock generator will ignore

Hsync inputs when COAST is LOW, and continue

operating at the same nominal frequency until COAST

goes HIGH.

Active HIGH means that the clock generator will ignore

Hsync inputs when COAST is HIGH, and continue

operating at the same nominal frequency until COAST

goes LOW.

This function needs to be used along with the COAST

polarity override bit (Bit 4).

The power-up default value is CSTPOL = 1.

Seek Mode Override

This bit is used to either allow or disallow the low-power

mode. The low-power mode (seek mode) occurs when

there are no signals on any of the Sync inputs.

Table XXI. Seek Mode Override Settings

Select

Result

Allow Seek Mode

Disallow Seek Mode

The default for this register is 1.

PWRDN

This bit is used to put the chip in power-down mode. In this

mode the chip’s power dissipation is reduced to a fraction

of the typical power (see the Electrical Characteristics

table for exact power dissipation). When in power-down,

the HSOUT, VSOUT, DATACK,

DATACK, and all 48

of the data outputs are put into a high impedance state.

(Note: the SOGOUT output is not put into high imped-

ance.) Circuit blocks that continue to be active during

power-down include the voltage references, sync process-

ing, sync detection, and the serial register. These blocks

facilitate a fast start-up from power-down.

Table XXII. Power-Down Settings

Select

Result

Power-Down

Normal Operation

The default for this register is 1.

7-3

Sync-on-Green Slicer Threshold

This register allows the comparator threshold of the Sync-

on-Green slicer to be adjusted. This register adjusts it in

steps of 10 mV, with the minimum setting equaling 10 mV

and the maximum setting equaling 330 mV.

The default setting is 15 and corresponds to a threshold

value of 0.16 V.

Red Clamp Select

A bit that determines whether the red channel is clamped

to ground or to midscale. For RGB video, all three chan-

nels are referenced to ground. For YcbCr (or YUV), the

Y channel is referenced to ground, but the CbCr channels

are referenced to midscale. Clamping to midscale actually

clamps to Pin 9.

Table XXIII. Red Clamp Select Settings

Clamp

Function

Clamp to Ground

Clamp to Midscale (Pin 9)

The default setting for this register is 0.

Blue Clamp Select

A bit that determines whether the blue channel is clamped

to ground or to midscale. Clamping to midscale actually

clamps to Pin 24.

Table XXIV. Blue Clamp Select Settings

Clamp

Function

Clamp to Ground

Clamp to Midscale (Pin 24)

The default setting for this register is 0.

7:0

Sync Separator Threshold

This register is used to set the responsiveness of the sync

separator. It sets how many internal 5 MHz clock periods

the sync separator must count to before toggling high or

low. It works like a low-pass filter to ignore Hsync pulses

in order to extract the Vsync signal. This register should

be set to some number greater than the maximum Hsync

pulsewidth. Note: the sync separator threshold uses an

internal dedicated clock with a frequency of approxi-

mately 5 MHz.

The default for this register is 32.

7-0

Pre-COAST

This register allows the COAST signal to be applied prior

to the Vsync signal. This is necessary in cases where pre-

equalization pulses are present. The step size for this

control is one Hsync period.

The default is 0.

7-0

Post-COAST

This register allows the COAST signal to be applied

following to the Vsync signal. This is necessary in cases

where post-equalization pulses are present. The step size

for this control is one Hsync period.

The default is 0.

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