AD9888SLASHPCB datasheet(26/32 Pages) AD

26 / 32 page

REV. A

AD9888

–26–

2-WIRE SERIAL CONTROL PORT

A 2-wire serial interface control interface is provided. Up to two

AD9888 devices may be connected to the 2-wire serial interface,

with each device having a unique address.

The 2-wire serial interface comprises a clock (SCL) and a bidirec-

tional data (SDA) pin. The AD9888 acts as a slave for receiving

and transmitting data over the serial interface. When the serial

interface is not active, the logic levels on SCL and SDA are

pulled HIGH by external pull-up resistors.

Data received or transmitted on the SDA line must be stable for

the duration of the positive-going SCL pulse. Data on SDA must

change only when SCL is LOW. If SDA changes state while SCL is

HIGH, the serial interface interprets that action as a start or stop

sequence.

There are six components to serial bus operation:

Start signal

Slave address byte

Base register address byte

Data byte to read or write

Stop signal

When the serial interface is inactive (SCL and SDA are HIGH),

communications are initiated by sending a start signal. The start

signal is a HIGH-to-LOW transition on SDA while SCL is HIGH.

This signal alerts all slaved devices that a data transfer sequence

is coming.

The first eight bits of data transferred after a start signal comprise

a 7-bit slave address (the first seven bits) and a single R/

W bit

(the eighth bit). The R/

W bit indicates the direction of data transfer,

read from (1) or write to (0) the slave device. If the transmitted slave

address matches the address of the device (set by the state of the A0

input pin in Table XLI), the AD9888 acknowledges by bringing

SDA LOW on the ninth SCL pulse. If the addresses do not match,

the AD9888 does not acknowledge

Table XLI. Serial Port Addresses

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0110

Data Transfer via Serial Interface

For each byte of data read or written, the MSB is the first bit of

the sequence.

If the AD9888 does not acknowledge the master device during a

write sequence, the SDA remains HIGH so the master can

generate a stop signal. If the master device does not acknowledge

the AD9888 during a read sequence, the AD9888 interprets this

as “end of data.” The SDA remains HIGH so the master can

generate a stop signal.

Writing data to specific control registers of the AD9888 requires

that the 8-bit address of the control register of interest be writ-

ten after the slave address has been established. This control

tions. The base address autoincrements by one for each byte of

data written after the data byte intended for the base address. If

more bytes are transferred than there are available addresses, the

address will not increment and remain at its maximum value of

19h. Any base address higher than 19h will not produce an

ACKnowledge signal.

Data are read from the control registers of the AD9888 in a

similar manner. Reading requires two data transfer operations.

The base address must be written with the R/

W bit of the slave

address byte LOW to set up a sequential read operation.

Reading (the R/

W bit of the slave address byte HIGH) begins at

the previously established base address. The address of the read

To terminate a read/write sequence to the AD9888, a stop sig-

nal must be sent. A stop signal comprises a LOW-to-HIGH

transition of SDA while SCL is HIGH.

A repeated start signal occurs when the master device driving

the serial interface generates a start signal without first generat-

ing a stop signal to terminate the current communication. This

is used to change the mode of communication (read, write)

between the slave and master without releasing the serial inter-

face lines.

Serial Interface Read/Write Examples

Write to One Control Register

Start Signal

Slave Address Byte (R/

W Bit = LOW)

Base Address Byte

Data Byte to Base Address

Stop Signal

Write to Four Consecutive Control Registers

Start Signal

Slave Address Byte (R/

W Bit = LOW)

Base Address Byte

Data Byte to Base Address

Data Byte to (Base Address + 1)

Data Byte to (Base Address + 2)

Data Byte to (Base Address + 3)

Stop Signal

Read from One Control Register

Start Signal

Slave Address Byte (R/

W Bit = LOW)

Base Address Byte

Start Signal

Slave Address Byte (R/

W Bit = HIGH)

Data Byte from Base Address

Stop Signal

Read from Four Consecutive Control Registers

Start Signal

Slave Address Byte (R/

W bit = LOW)

Base Address Byte

Start Signal

Slave Address Byte (R/

W Bit = HIGH)

Data Byte from Base Address

Data Byte from (Base Address + 1)

Data Byte from (Base Address + 2)

Data Byte from (Base Address + 3)

Stop Signal

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