AD9888SLASHPCB datasheet(22/32 Pages) AD

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Table XI. Active Hsync Override Settings

Override

Result

Auto determines the active interface.

Override, Bit 3 determines the active interface.

The default for this register is 0.

Active Hsync Select

This bit is used under two conditions. It is used to select

the active Hsync when the override bit is set (Bit 4). Alter-

nately, it is used to determine the active Hsync when not

overriding but both Hsyncs are detected.

Table XII. Active Hsync Select Settings

Select

Result

Hsync Input

Sync-on-Green Input

The default for this register is 0.

Vsync Output Invert

A bit that inverts the polarity of the Vsync output. Table

XIII shows the effect of this option.

Table XIII. Vsync Output Polarity Settings

Setting

SYNC

Invert

Don’t Invert

The default setting for this register is 0.

Active Vsync Override

This bit is used to override the automatic Vsync selection.

To override, set this bit to Logic 1. When overriding, the

active interface is set via Bit 0 in this register.

Table XIV. Active Vsync Override Settings

Override

Result

Auto determines the active Vsync.

Override, Bit 0 determines the active Vsync.

The default for this register is 0.

Active Vsync Select

This bit is used to select the active Vsync when the over-

ride bit is set (Bit 1).

Table XV. Active Vsync Select Settings

Select

Result

Vsync Input

Sync Separator Output

The default for this register is 0.

Clamp Input Signal Source

A bit that determines the source of clamp timing.

Table XVI. Clamp Input Signal Source Settings

External Clamp

Function

Internally Generated Clamp

Externally Provided Clamp Signal

A 0 enables the clamp timing circuitry controlled by clamp

placement and clamp duration. The clamp position and

duration is counted from the leading edge of Hsync.

A 1 enables the external CLAMP input pin. The three

channels are clamped when the CLAMP signal is active.

The polarity of CLAMP is determined by the Clamp

Polarity bit (Register 0Fh, Bit 6).

The power-up default value is External Clamp = 0.

Clamp Input Signal Polarity

A bit that determines the polarity of the externally pro-

vided CLAMP signal.

Table XVII. Clamp Input Signal Polarity Settings

Clamp Polarity

Function

Active LOW

Active HIGH

A Logic 1 means that the circuit will clamp when CLAMP

is LOW, and it will pass the signal to the ADC when

CLAMP is HIGH.

A Logic 0 means that the circuit will clamp when CLAMP

is HIGH, and it will pass the signal to the ADC when

CLAMP is LOW.

The power-up default value is Clamp Polarity = 1.

COAST Select

This bit is used to select the active coast source. The

choices are the coast input pin or Vsync. If Vsync is selected,

the additional decision of using the Vsync input pin or the

output from the sync separator needs to be made (Register

0E, Bits 1, 0).

Table XVIII. COAST Source Selection Settings

Select

Result

COAST Input Pin

Vsync (See above text.)

The default for this register is 0.

COAST Input Polarity Override

This register is used to override the internal circuitry that

determines the polarity of the coast signal going into the

PLL.

Table XIX. COAST Input Polarity Override Settings

Override Bit

Result

COAST Polarity Determined by Chip

COAST Polarity Determined by User

The default for coast polarity override is 0.

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