AD9888SLASHPCB datasheet(24/32 Pages) AD

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REV. A

AD9888

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Hsync Detect

This bit is used to indicate when activity is detected on

the selected Hsync input pin. If HSYNC is held high or

low, activity will not be detected.

Table XXV. Hsync Detection Results

Detect

Function

No Activity Detected

Activity Detected

The sync processing block diagram shows where this

function is implemented.

AHS – Active Hsync

This bit indicates which Hsync input source is being used

by the PLL (Hsync input or Sync-on-Green). Bits 7 and 1

in this register are what determine which source is used. If

both Hsync and SOG are detected, the user can determine

which has priority via Bit 3 in Register 0EH. The user can

override this function via Bit 4 in Register 0EH. If the

override bit is set to Logic 1, then this bit will be forced to

whatever the state of Bit 3 in register 0EH is set to.

Table XXVI. Active Hsync Results

Bit 7

Bit 1

Bit 4, Reg

(Hsync

(SOG

OEH

Detect)

(Override)

AHS

Bit 3 in 0EH

AHS = 0 means use the HSYNC pin input for HSYNC.

AHS = 1 means use the SOG pin input for HSYNC.

The override bit is in Register 0EH, Bit 4.

Detected Hsync Input Polarity Status

This bit reports the status of the HSYNC input polarity

detection circuit. It can be used to determine the polarity

of the HSYNC input. The detection circuit’s location is

shown in the Sync Processing Block Diagram (Figure 25).

Table XXVII. Detected Hsync Input Polarity Status

HSYNC Polarity Status

Result

Hsync Polarity is Negative.

Hsync Polarity is Positive.

Vsync Detect

This bit is used to indicate when activity is detected on

the selected Vsync input pin. If Vsync is held high or low,

activity will not be detected.

Table XXVIII. Vsync Detection Results

Detect

Function

No Activity Detected

Activity Detected

The sync processing block diagram (Figure 25) shows where

this function is implemented.

AVS – Active Vsync

This bit indicates which Vsync source is being used; the

Vsync input or the output from the sync separator. Bit 4

in this register is what determines which is active. If both

Vsync and SOG are detected, the user can determine

which has priority via Bit 0 in Register 0EH. The user can

override this function via Bit 1 in Register 0EH. If the

override bit is set to Logic 1, this bit will be forced to

whatever the state of Bit 0 in Register 0EH is set to.

Table XXIX. Active Vsync Results

Bit 5 (Vsync Detect)

Override

AVS

Bit 0 in 0EH

AVS = 1 means Sync separator.

AVS = 0 means Vsync input.

The override bit is in Register 0EH, Bit 1.

Detected Vsync Output Polarity Status

This bit reports the status of the Vsync output polarity

detection circuit. It can be used to determine the polarity

of the Vsync input. The detection circuit’s location is

shown in the Sync Processing Block Diagram (Figure 25).

Table XXX. Detected Vsync Input Polarity Status

Vsync Polarity Status

Result

Vsync Polarity is Active Low

Vsync Polarity is Active High

Sync-on-Green Detect

This bit is used to indicate when Sync activity is detected

on the selected Sync-on-Green input pin.

Table XXXI. Sync-on-Green Detection Results

Detect

Function

No Activity Detected

Activity Detected

The Sync Processing Block Diagram (Figure 25) shows

where this function is implemented.

Detected COAST Polarity Status

This bit reports the status of the coast input polarity de-

tection circuit. It can be used to determine the polarity

of the COAST input. The detection circuit’s location is

shown in Figure 25.

Table XXXII. Detected COAST Input Polarity Status

HSYNC Polarity Status

Result

COAST Polarity is Negative.

COAST Polarity is Positive.

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