AD9888SLASHPCB datasheet(25/32 Pages) AD

25 / 32 page

REV. A

AD9888

–25–

MODE CONTROL 1

Channel Mode

A bit that determines whether all pixels are presented to a

single port (A), or alternating pixels are demultiplexed to

Ports A and B.

Table XXXIII. Channel Mode Settings

DEMUX

Function

All data goes to Port A.

Alternate pixels go to Port A and Port B.

When DEMUX = 0, Port B outputs are in a high-

impedance state. The maximum data rate for single-port

mode is 110 MHz. The timing diagrams starting with

Figure 13 show the effects of this option.

The power-up default value is 1.

Output Mode

A bit that determines whether all pixels are presented to Port A

and Port B simultaneously on every second DATACK

rising edge, or alternately on Port A and Port B on successive

DATACK rising edges.

Table XXXIV. Output Mode Settings

PARALLEL

Function

Data is interleaved.

Data is simultaneous on every other data

clock.

When in single port mode (DEMUX = 0), this bit is

ignored. The timing diagrams (Figure 17) show the effects

of this option.

The power-up default value is PARALLEL = 1.

Output Port Phase

One bit that determines whether even pixels or odd pixels

go to Port A.

Table XXXV. Output Port Phase Settings

OUTPHASE

First Pixel after Hsync

Port A

Port B

In normal operation (OUTPHASE = 0), when operating

in dual-port output mode (DEMUX = 1), the first sample

after the Hsync leading edge is presented at Port A. Every

subsequent ODD sample appears at Port A. All EVEN

samples go to Port B.

When OUTPHASE = 1, these ports are reversed and the

first sample goes to Port B.

When DEMUX = 0, this bit is ignored as data always

comes out of only Port A.

4:2:2 Output Mode Select

A bit that configures the output data in 4:2:2 mode. This

mode can be used to reduce the number of data lines used

from 24 down to 16 for applications using YUV, YCbCr,

or YPbPr graphics signals. A timing diagram for this mode

is shown in Figure 12. Recommended input and output

configurations are shown in Table XXXVII. In 4:2:2

mode, the red and blue channels can be interchanged to

help satisfy board layout or timing requirements, but the

green channel must be configured for Y.

Table XXXVI. 4:2:2 Output Mode Select

Select

Output Mode

4:4:4

4:2:2

Table XXXVII. 4:2:2 Input/Output Configuration

Channel

Input Connection

Output Format

Red

U/V

Green

Blue

High Impedance

Input Mux Control

A bit that selects either analog inputs from Channel 0 or

the analog inputs from Channel 1.

Table XXXVIII. Input Mux Control

Control

Channel Selected

Channel 0

Channel 1

2-1

Analog Bandwidth Control

Two bits that select the analog bandwidth.

Table XXXIX. Analog Bandwidth Control

Bit 2

Bit 1

Analog Bandwidth

500 MHz

300 MHz

150 MHz

75 MHz

External Clock Select

A bit that determines the source of the pixel clock.

Table XL. External Clock Select Settings

EXTCLK

Function

Internally Generated Clock

Externally Provided Clock Signal

A Logic 0 enables the internal PLL that generates the

pixel clock from an externally provided HSYNC.

A Logic 1 enables the external CKEXT input pin. In this

mode, the PLL Divide Ratio (PLLDIV) is ignored. The

clock phase adjust (PHASE) is still functional.

The power-up default value is EXTCLK = 0.

AD9888/PCB 数据表(PDF) 25 Page - Analog Devices

AD9888/PCB 数据表(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

数据表下载

链接网址

AD9888/PCB 数据表(PDF) 25 Page - Analog Devices

AD9888/PCB 数据表(HTML) 25 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

数据表 下载

链接网址

数据表下载