APFCON datasheet(42/222 Pages) MICROCHIP

42 / 222 page

MCP19111

DS22331A-page 42

 2013 Microchip Technology Inc.

6.7

Slope Compensation

A negative voltage slope is added to the output of the

error amplifier. This is done to prevent subharmonic

instability when:

the operating duty cycle is greater than 50%

wide changes in the duty cycle occur.

The amount of negative slope added to the error ampli-

fier output is controlled by Register 6-7.

The slope compensation is enabled by setting the

SLCPBY bit in the ABECON register.

6.7.1

SLPS<3:0> CONFIGURATION

The SLPS<3:0> directly controls the

V/t of the

added ramp. This byte should be set proportional to

the switching frequency according to the following

equation.

6.7.2

SLPG<3:0> CONFIGURATION

The SLPG<3:0> controls the amplitude of the added

ramp. The values listed above correspond to a 50%

duty cycle waveform and is true only if the SLPS<3:0>

bits are set according to the equation in Section 6.7.1

“SLPS<3:0> Configuration”. If less amplitude is

required, the SLPS<3:0> bits can be adjusted to a

lower switching frequency.

SLPCRCON: SLOPE COMPENSATION RAMP CONTROL REGISTER

R/W-x

SLPG3

SLPG2

SLPG1

SLPG0

SLPS3

SLPS2

SLPS1

SLPS0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-4

SLPG<3:0>: Slope Compensation Amplitude Configuration bits

0000

= 0.017 VPK-PK, measured for 50% duty cycle waveform

0001

= 0.022 VPK-PK, measured for 50% duty cycle waveform

0010

= 0.030 VPK-PK, measured for 50% duty cycle waveform

0011

= 0.040 VPK-PK, measured for 50% duty cycle waveform

0100

= 0.053 VPK-PK, measured for 50% duty cycle waveform

0101

= 0.070 VPK-PK, measured for 50% duty cycle waveform

0110

= 0.094 VPK-PK, measured for 50% duty cycle waveform

0111

= 0.125 VPK-PK, measured for 50% duty cycle waveform

1000

= 0.170 VPK-PK, measured for 50% duty cycle waveform

1001

= 0.220 VPK-PK, measured for 50% duty cycle waveform

1010

= 0.300 VPK-PK, measured for 50% duty cycle waveform

1011

= 0.400 VPK-PK, measured for 50% duty cycle waveform

1100

= 0.530 VPK-PK, measured for 50% duty cycle waveform

1101

= 0.700 VPK-PK, measured for 50% duty cycle waveform

1110

= 0.940 VPK-PK, measured for 50% duty cycle waveform

1111

= 1.250 VPK-PK, measured for 50% duty cycle waveform

bit 3-0

SLPS<3:0>: Slope Compensation

V/t Configuration bits

100 000



---------------------





–

Where:

FSW = Device switching frequency

n = Decimal equivalent of SLPS<3:0>

APFCON 数据表(PDF) 42 Page - Microchip Technology

APFCON 数据表(HTML) 42 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载