APFCON datasheet(119/222 Pages) MICROCHIP

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 2013 Microchip Technology Inc.

DS22331A-page 119

MCP19111

20.0

INTERRUPT-ON-CHANGE

Each PORTGPA and PORTGPB pin is individually

configurable as an interrupt-on-change pin. Control bits

IOCA and IOCB enable or disable the interrupt function

for each pin. Refer to Register 20-1 and Register 20-2.

The interrupt-on-change is disabled on a Power-on

Reset.

The interrupt-on-change on GPA5 is disabled when

configured as MCLR pin in the Configuration Word.

For enabled interrupt-on-change pins, the values are

compared with the old value latched on the last read of

PORTGPA or PORTGPB. The mismatched outputs of

the last read of all the PORTGPA and PORTGPB pins

are OR’ed together to set the Interrupt-on-Change

Interrupt Flag bit (IOCF) in the INTCON register

(Register 15-1).

20.1

Enabling the Module

To allow individual port pins to generate an interrupt, the

IOCIE bit of the INTCON register must be set. If the

IOCIE bit is disabled, the edge detection on the pin will

still occur, but an interrupt will not be generated.

20.2

Individual Pin Configuration

To enable a pin to detect an interrupt-on-change, the

associated IOCAx or IOCBx bit of the IOCA or IOCB

20.3

Clearing Interrupt Flags

The user, in the Interrupt Service Routine, clears the

interrupt by:

Any read of PORTGPA or PORTGPB AND

Clear flag bit IOCF. This will end the mismatch

condition;

Any write of PORTGPA or PORTGPB AND

Clear flag bit IOCF will end the mismatch

condition;

A mismatch condition will continue to set flag bit IOCF.

Reading PORTGPA or PORTGPB will end the

mismatch condition and allow flag bit IOCF to be

cleared. The latch holding the last read value is not

affected by a MCLR Reset. After this Reset, the IOCF

flag will continue to be set if a mismatch is present.

20.4

Operation in Sleep

The interrupt-on-change interrupt sequence will wake

the device from Sleep mode, if the IOCE bit is set.

Note:

If a change on the I/O pin should occur

when

any

PORTGPA

PORTGPB

operation is being executed, then the

IOCF interrupt flag may not get set.

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