APFCON datasheet(168/222 Pages) MICROCHIP

168 / 222 page

MCP19111

DS22331A-page 168

 2013 Microchip Technology Inc.

FIGURE 27-17:

BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

27.5.3

WCOL STATUS FLAG

If the user writes the SSPBUF when a Start, Restart,

Stop, Receive or Transmit sequence is in progress, the

WCOL is set and the contents of the buffer are

unchanged (the write does not occur). Any time the

WCOL bit is set, it indicates that an action on SSPBUF

was attempted while the module was not Idle.

27.5.4

I2C MASTER MODE START

CONDITION TIMING

To initiate a Start condition, the user sets the Start

Enable bit, SEN bit of the SSPCON2 register. If the

SDA and SCL pins are sampled high, the Baud Rate

Generator

reloaded

with

the

contents

SSPADD<7:0> and starts its count. If SCL and SDA

are both sampled high when the Baud Rate Generator

times out (TBRG), the SDA pin is driven low. The action

of the SDA being driven low while SCL is high is the

Start condition and causes the S bit of the SSPSTAT1

Generator

reloaded

with

the

contents

SSPADD<7:0> and resumes its count. When the Baud

Rate Generator times out (TBRG), the SEN bit of the

SSPCON2 register will be automatically cleared by

hardware; the Baud Rate Generator is suspended,

leaving the SDA line held low and the Start condition is

complete.

FIGURE 27-18:

FIRST START BIT TIMING

SDA

SCL

SCL deasserted but slave holds

DX ‚ – 1

BRG

SCL is sampled high, reload takes

place and BRG starts its count

03h

02h

01h

00h (hold off)

03h

02h

Reload

BRG

Value

SCL low (clock arbitration)

SCL allowed to transition high

BRG decrements on

Q2 and Q4 cycles

Note:

Because queueing of events is not

allowed, writing to the lower 5 bits of

SSPCON2 is disabled until the Start

condition is complete.

Note 1: If at the beginning of the Start condition,

the SDA and SCL pins are already sam-

pled low, or if during the Start condition,

the SCL line is sampled low before the

SDA line is driven low, a bus collision

occurs, the Bus Collision Interrupt Flag,

BCLIF, is set, the Start condition is

aborted and the I2C module is reset into

its Idle state.

2: The Philips I2C Specification states that a

bus collision cannot occur on a Start.

SDA

SCL

TBRG

1st bit

2nd bit

TBRG

SDA = 1,

At completion of Start bit,

SCL = 1

Write to SSPBUF occurs here

TBRG

hardware clears SEN bit

TBRG

Write to SEN bit occurs here

Set S bit (SSPSTAT<3>)

and sets SSPIF bit

APFCON 数据表(PDF) 168 Page - Microchip Technology

APFCON 数据表(HTML) 168 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

APFCON 数据表(PDF) 168 Page - Microchip Technology

APFCON 数据表(HTML) 168 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载