APFCON datasheet(185/222 Pages) MICROCHIP

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 2013 Microchip Technology Inc.

DS22331A-page 185

MCP19111

SSPCON3: SSP CONTROL REGISTER 3

R-0/0

R/W-0/0

ACKTIM

PCIE

SCIE

BOEN

SDAHT

SBCDE

AHEN

DHEN

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

ACKTIM: Acknowledge Time Status bit (I2C mode only)(2)

= Indicates the I2C bus is in an Acknowledge sequence, set on the 8th falling edge of SCL clock

= Not an Acknowledge sequence, cleared on the 9th rising edge of SCL clock

bit 6

PCIE: Stop Condition Interrupt Enable bit (I2C mode only)

= Enable interrupt on detection of Stop condition

= Stop detection interrupts are disabled(1)

bit 5

SCIE: Start Condition Interrupt Enable bit (I2C mode only)

= Enable interrupt on detection of Start or Restart conditions

= Start detection interrupts are disabled(1)

bit 4

BOEN: Buffer Overwrite Enable bit

In I2C Master mode:

This bit is ignored.

In I2C Slave mode:

= SSPBUF is updated and ACK is generated for a received address/data byte, ignoring the state

of the SSPOV bit only if the BF bit = 0.

= SSPBUF is only updated when SSPOV is clear

bit 3

SDAHT: SDA Hold Time Selection bit

= Minimum of 300 ns hold time on SDA after the falling edge of SCL

= Minimum of 100 ns hold time on SDA after the falling edge of SCL

bit 2

SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)

If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCLIF

bit of the PIR2 register is set, and bus goes Idle

= Enable slave bus collision interrupts

= Slave bus collision interrupts are disabled

bit 1

AHEN: Address Hold Enable bit (I2C Slave mode only)

= Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the

SSPCON1 register will be cleared and the SCL will be held low.

= Address holding is disabled

bit 0

DHEN: Data Hold Enable bit (I2C Slave mode only)

= Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit

of the SSPCON1 register and SCL is held low.

= Data holding is disabled

Note 1:

This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.

The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.

APFCON 数据表(PDF) 185 Page - Microchip Technology

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