LSM330DLC datasheet(45/66 Pages) STMICROELECTRONICS

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LSM330DLC

Doc ID 022162 Rev 2

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8.6

CTRL_REG6_A (25h)

8.7

REFERENCE/DATACAPTURE_A (26h)

8.8

STATUS_REG_A (27h)

LIR_INT1

Latch interrupt request on INT1_SRC register, with INT1_SRC register

cleared by reading INT1_SRC itself. Default value: 0.

(0: interrupt request not latched; 1: interrupt request latched)

D4D_INT1

4D enable: 4D detection is enabled on INT1 when 6D bit on INT1_CFG is set

to 1.

Table 30.

CTRL_REG5_A description (continued)

Table 31.

CTRL_REG6_A register

I2_CLICKen

I2_INT1

0(1)

This bit must be set to ‘0’ for correct operation.

BOOT_I2

0(1)

H_LACTIVE

Table 32.

CTRL_REG6 description

I2_CLICKen

Click interrupt on INT2_A. Default value 0.

I2_INT1

Interrupt 1 function enabled on INT2_A. Default 0.

BOOT_I2

Boot on INT2_A.

H_LACTIVE

0: interrupt active high; 1: interrupt active low.

Table 33.

REFERENCE_A register

Ref7

Ref6

Ref5

Ref4

Ref3

Ref2

Ref1

Ref0

Table 34.

REFERENCE register description

Ref 7-Ref0

Reference value for interrupt generation. Default value: 0

Table 35.

STATUS_REG_A register

ZYXOR

ZOR

YOR

XOR

ZYXDA

ZDA

YDA

XDA

Table 36.

STATUS_REG_A register description

ZYXOR

X, Y and Z axis data overrun. Default value: 0

(0: no overrun has occurred; 1: a new set of data has overwritten the previous data)

ZOR

Z axis data overrun. Default value: 0

(0: no overrun has occurred; 1: new data for the Z-axis has overwritten the previous data)

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