ADE7953ACPZ datasheet(58/68 Pages) AD

58 / 68 page

ADE7953

Data Sheet

Rev. A | Page 58 of 68

CHECKSUM REGISTER

The ADE7953 includes a 32-bit checksum register, CRC

(Address 0x37F), which warns the user if any of the important

configuration, control, or calibration registers are modified. The

checksum register helps to ensure that the meter configuration

is not modified from its desired state during normal operation.

Table 12 lists the registers included in the checksum. An

additional eight internal reserved registers are also included in

the checksum. The ADE7953 computes the cyclic redundancy

check (CRC) based on the IEEE 802.3 standard. The contents of

the registers are introduced one by one into a linear feedback

shift register (LFSR) based generator, starting with the least

significant bit. The 32-bit result is written to the CRC register.

Figure 75 shows how the LFSR works. The registers shown in

Table 12 and the eight 8-bit reserved internal registers form the

bits [a1023, a1022,…, a0] used by LFSR. Bit a0 is the least significant

bit of the first register to enter LFSR; Bit a1023 is the most signifi-

cant bit of the last register to enter LFSR.

The formulas that govern LFSR are as follows:

bi(0) = 1, i = 0, 1, 2, …, 31, the initial state of the bits that form

the CRC. Bit b0 is the least significant bit, and Bit b31 is the most

significant.

bi(0) = 1, i = 0, 1, 2, …, 31, the initial state of the bits that form

the CRC. Bit b0 is the least significant bit, and Bit b31 is the most

significant.

gi, i = 0, 1, 2, …, 31 are the coefficients of the generating

polynomial defined by the IEEE802.3 standard as follows:

G(x) = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 +

x4 + x2 + x + 1.

g0 = g1 = g2 = g4 = g5 = g7 = 1

g8 = g10 = g11 = g12 = g16 = g22 = g26 = g31 = 1

(50)

All of the other gi coefficients are equal to 0.

FB(j) = aj – 1 XOR b31(j – 1)

(51)

b0(j) = FB(j) AND g0

(52)

bi(j) = FB(j) AND gi XOR bi − 1(j – 1), i = 1, 2, 3, ..., 31

(53)

Equation 51, Equation 52, and Equation 53 must be repeated for

j = 1, 2, …, 1024. The value written into the Checksum register

contains the Bit bi(1024), i = 0, 1, …, 31.

1023

LFSR

GENERATOR

ARRAY OF 1024 BITS

Figure 75. Checksum Register Calculation

LFSR

g31

b31

a255, a254,....,a2, a1, a0

Figure 76. LFSR Generator Used in Checksum Register Calculation

The CRC is disabled by default and can be enabled by setting

the CRC_ENABLE bit (Bit 8) of the CONFIG register

(Address 0x102). When this bit is set, the CRC is computed at

a rate of 6.99 kHz. Because the CRC is disabled by default, the

default value is 0xFFFFFFFF. Once enabled, with all registers at

their default value, the CRC is 0x48739163.The checksum can

be used to ensure that the registers included in the checksum

are not inadvertently changed by periodically reading the value

in the CRC register (Address 0x37F) after the meter is

configured.

If two consecutive readings differ, it can be assumed that one

of the registers has changed value and, therefore, the configuration

of the ADE7953 has changed. Note that since the CRC updates at

a rate of 6.99 kHz, consecutive reads should be at least 143 μs

(1/6.99 kHz) apart. The recommended response is to issue a

hardware/software reset, which resets all ADE7953 registers,

including reserved registers, to their default values. The

ADE7953 should then be reconfigured with the design-specific

settings.

An interrupt associated with the checksum feature can provide

an external warning signal on the IRQ pin if the CRC register

value changes after initial configuration. This interrupt is dis-

abled by default and can be enabled by setting the CRC bit (Bit 21)

in the IRQENA register (Address 0x22C and Address 0x32C).

When this interrupt is enabled, an external interrupt is issued

if the CRC value changes from the value that it held at the time

that it was enabled.

ADE7953ACPZ 数据表(PDF) 58 Page - Analog Devices

ADE7953ACPZ 数据表(HTML) 58 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

数据表下载