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ADE7953ACPZ 数据表(PDF) 62 Page - Analog Devices

部件名 ADE7953ACPZ
功能描述  Single Phase, Multifunction Metering IC with Neutral Current Measurement
PDF  68 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE7953ACPZ 数据表(HTML) 62 Page - Analog Devices

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ADE7953
Data Sheet
Rev. A | Page 62 of 68
Address
24-Bit
32-Bit
Register Name
R/W
Default
Type
Register Description
0x28C
0x38C
BIGAIN
R/W
0x400000
Unsigned
Current channel gain (Current Channel B)
0x28D
0x38D
Reserved
R/W
0x400000
Unsigned
This register should not be modified.
0x28E
0x38E
BWGAIN
R/W
0x400000
Unsigned
Active power gain (Current Channel B)
0x28F
0x38F
BVARGAIN
R/W
0x400000
Unsigned
Reactive power gain (Current Channel B)
0x290
0x390
BVAGAIN
R/W
0x400000
Unsigned
Apparent power gain (Current Channel B)
0x291
0x391
Reserved
R/W
0x000000
Signed
This register should not be modified.
0x292
0x392
BIRMSOS
R/W
0x000000
Signed
IRMS offset (Current Channel B)
0x293
0x393
Reserved
R/W
0x000000
Unsigned
This register should not be modified.
0x294
0x394
Reserved
R/W
0x000000
Unsigned
This register should not be modified.
0x295
0x395
BWATTOS
R/W
0x000000
Signed
Active power offset correction (Current Channel B)
0x296
0x396
BVAROS
R/W
0x000000
Signed
Reactive power offset correction (Current Channel B)
0x297
0x397
BVAOS
R/W
0x000000
Signed
Apparent power offset correction (Current Channel B)
0x2FF
0x3FF
LAST_RWDATA
R
0x000000
Unsigned
Contains the data from the last successful 24-bit/32-bit
register communication
ADE7953 REGISTER DESCRIPTIONS
Table 16. DISNOLOAD Register (Address 0x001)
Bits
Bit Name
Default
Description
0
DIS_APNLOAD
0
1 = disable the active power no-load feature on Current Channel A and Current Channel B
1
DIS_VARNLOAD
0
1 = disable the reactive power no-load feature on Current Channel A and Current Channel B
2
DIS_VANLOAD
0
1 = disable the apparent power no-load feature on Current Channel A and Current Channel B
Table 17. LCYCMODE Register (Address 0x004)
Bits
Bit Name
Default
Description
0
ALWATT
0
0 = disable active energy line cycle accumulation mode on Current Channel A
1 = enable active energy line cycle accumulation mode on Current Channel A
1
BLWATT
0
0 = disable active energy line cycle accumulation mode on Current Channel B
1 = enable active energy line cycle accumulation mode on Current Channel B
2
ALVAR
0
0 = disable reactive energy line cycle accumulation mode on Current Channel A
1 = enable reactive energy line cycle accumulation mode on Current Channel A
3
BLVAR
0
0 = disable reactive energy line cycle accumulation mode on Current Channel B
1 = enable reactive energy line cycle accumulation mode on Current Channel B
4
ALVA
0
0 = disable apparent energy line cycle accumulation mode on Current Channel A
1 = enable apparent energy line cycle accumulation mode on Current Channel A
5
BLVA
0
0 = disable apparent energy line cycle accumulation mode on Current Channel B
1 = enable apparent energy line cycle accumulation mode on Current Channel B
6
RSTREAD
1
0 = disable read with reset for all registers
1 = enable read with reset for all registers
Table 18. CONFIG Register (Address 0x102)
Bits
Bit Name
Default
Description
0
INTENA
0
1 = integrator enable (Current Channel A)
1
INTENB
0
1 = integrator enable (Current Channel B)
2
HPFEN
1
1 = HPF enable (all channels)
3
PFMODE
0
0 = power factor is based on instantaneous powers
1 = power factor is based on line cycle accumulation mode energies
4
REVP_CF
0
0 = REVP is updated on CF1
1 = REVP is updated on CF2
5
REVP_PULSE
0
0 = REVP is high when reverse polarity is true, low when reverse polarity is false
1 = REVP outputs a 1 Hz pulse when reverse polarity is true and is low when reverse polarity is false
6
ZXLPF
0
0 = ZX LPF is enabled
1 = ZX LPF is disabled
7
SWRST
0
Setting this bit enables a software reset



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