ADE7953ACPZ datasheet(19/68 Pages) AD

19 / 68 page

Data Sheet

ADE7953

Rev. A | Page 19 of 68

THEORY OF OPERATION

ANALOG INPUTS

The ADE7953 includes three analog inputs that form two current

channels and one voltage channel. In a standard configuration,

Current Channel A is used to measure the phase current, and

Current Channel B is used to measure the neutral current. The

voltage channel input measures the difference between the phase

voltage and the neutral voltage. The ADE7953 can, however, be

used with alternative voltage and current combinations as long as

the analog input specifications described in this section are met.

Current Channel A

Current Channel A is a fully differential voltage input that is

designed to be used with a current sensor. This input is driven

by two pins: IAP (Pin 5) and IAN (Pin 6). The maximum differ-

ential voltage that can be applied to IAP and IAN is ±500 mV.

A common-mode voltage of less than ±25 mV is recommended.

Common-mode voltages in excess of this recommended value

may limit the available dynamic range. A programmable gain

amplifier (PGA) stage is provided on Current Channel A with

gain options of 1, 2, 4, 8, 16, and 22 (see Table 6).

The maximum full-scale input of Current Channel A is ±250 mV

when using a single-ended configuration and, therefore, when

using a gain setting of 1, the dynamic range is limited. The Current

Channel A gain is configured by writing to the PGA_IA register

(Address 0x008). By default, the Current Channel A PGA is set

to 1. A gain option of 22 is offered exclusively on Current

Channel A, allowing high accuracy measurement for signals of

very small amplitude. This configuration is particularly useful

when using small value shunt resistors or Rogowski coils.

Current Channel B

Current Channel B is a fully differential voltage input that is

designed to be used with a current sensor. This input is driven

by two pins: IBP (Pin 9) and IBN (Pin 10). The maximum differ-

ential voltage that can be applied to IBP and IBN is ±500 mV. A

common-mode voltage of less than ±25 mV is recommended.

Common-mode voltages in excess of this recommended value

may limit the available dynamic range. A PGA gain stage is

provided on Current Channel B with gain options of 1, 2, 4, 8,

and 16 (see Table 6). The Current Channel B gain is configured

by writing to the PGA_IB register (Address 0x009). By default,

the Current Channel B PGA is set to 1.

Voltage Channel

The voltage channel input a full differential input driven by

two pins: VP (Pin 12) and VN (Pin 11). The voltage channel

is typically connected in a single-ended configuration. The

maximum single-ended voltage that can be applied to VP is

±500 mV with respect to VN. A common-mode voltage of less

than ±25 mV is recommended. Common-mode voltages in

excess of this recommended value may limit the dynamic range

capabilities of the ADE7953. A PGA gain stage is provided on

the voltage channel with gain options of 1, 2, 4, 8, and 16 (see

Table 6).

The voltage channel gain is configured by writing to the PGA_V

set to 1.

Table 6. PGA Gain Settings

Gain

Full-Scale

Differential

Input (mV)

PGA_IA[2:0]

(Addr 0x008)

PGA_IB[2:0]

(Addr 0x009)

PGA_V[2:0]

(Addr 0x007)

±500

0001

000

±250

001

±125

010

±62.5

011

±31.25

100

±22.7

101

N/A

1 When a gain of 1 is selected on Current Channel A, the maximum pin input is

limited to ±250 mV. Therefore, when using a single-ended configuration, the

maximum input is ±250 mV with respect to AGND.

ANALOG-TO-DIGITAL CONVERSION

The analog-to-digital conversion in the ADE7953 is performed

by three second-order Σ-Δ modulators. For the sake of clarity,

the block diagram in Figure 36 shows the operation of a first-

order Σ-Δ modulator. The analog-to-digital conversion consists

of a Σ-Δ modulator followed by a low-pass filter stage.

DIGITAL

LOW-PASS

FILTER

–

CLKIN/4

INTEGRATOR

+VREF

–VREF

1-BIT DAC

LATCHED

COMPARATOR

ANALOG

LOW-PASS FILTER

.....10100101.....

–

Figure 36. Σ-Δ Conversion

The Σ-Δ modulator converts the input signal into a continuous

serial stream of 1s and 0s at a rate determined by the sampling

clock. The ADE7953 sampling clock is equal to 895 kHz

(CLKIN/4). The 1-bit DAC in the feedback loop is driven by the

serial data stream. The DAC output is subtracted from the input

signal. If the loop gain is high enough, the average value of the

DAC output (and, therefore, the bit stream) can approach that

of the input signal level. For any given input value in a single

sampling interval, the data from the 1-bit ADC is virtually

meaningless. A meaningful result is obtained only when a large

number of samples is averaged. This averaging is carried out

in the second part of the ADC, the digital low-pass filter. By

averaging a large number of bits from the modulator, the low-

pass filter can produce 24-bit data-words that are proportional

to the input signal level. The Σ-Δ converter uses two techniques—

oversampling and noise shaping—to achieve high resolution

from what is essentially a 1-bit conversion technique.

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