ADE7953ACPZ datasheet(29/68 Pages) AD

29 / 68 page

Data Sheet

ADE7953

Rev. A | Page 29 of 68

REACTIVE ENERGY CALCULATION

The ADE7953 achieves the integration of the reactive power

signal in two stages. In the first stage, the reactive power signals

are accumulated in an internal 48-bit register every 143 μs

(6.99 kHz) until an internal fixed threshold is reached. When

this threshold is reached, a pulse is generated and is accumu-

lated in 24-bit, user-accessible accumulation registers. The

internal threshold results in a maximum accumulation rate

of approximately 206.9 kHz with full-scale inputs. This process

occurs simultaneously on Current Channel A and Current

Channel B, and the resulting readings can be read in the

24-bit RENERGYA (Address 0x220 and Address 0x320) and

RENERGYB (Address 0x221 and Address 0x321) registers.

Both stages of the accumulation are signed and, therefore,

negative energy is subtracted from positive energy.

Note that the reactive energy register contents roll over to full-

scale negative (0x800000) and continue to increase in value

when the power or energy flow is positive. Conversely, if the

power is negative, the energy register underflows to full-scale

positive (0x7FFFFF) and continues to decrease in value.

RENERGYA and RENERGYB are read-with-reset registers

by default. This means that the contents of these registers are

reset to 0 after a read operation. This feature can be disabled

by clearing Bit 6 (RSTREAD) of the LCYCMODE register

(Address 0x004).

The ADE7953 includes two sets of interrupts that are triggered

when the reactive energy register is half full (positive or negative)

or when an overflow or underflow condition occurs. The first set

of interrupts is associated with the Current Channel A reactive

energy, and the second set of interrupts is associated with the

Current Channel B reactive energy. These interrupts are disabled

by default and can be enabled by setting the VAREHFA and

VAREOFA bits in the IRQENA register (Address 0x22C and

Address 0x32C) for Current Channel A, and the VAREHFB and

VAREOFB bits in the IRQENB register (Address 0x22F and

Address 0x32F) for Current Channel B.

Reactive Energy Integration Time Under Steady Load

The discrete time sample period (T) for the accumulation registers

is 4.83 μs (1/206.9 kHz). With full-scale sinusoidal signals on

the analog inputs and a phase shift of 90°, a pulse is generated

and added to the RENERGYA and RENERGYB registers every

4.83 μs, assuming that the AVARGAIN and BVARGAIN

registers are set to 0x00. The maximum positive value that can

be stored in the 24-bit RENERGYA and RENERGYB registers is

0x7FFFFF before the register overflows. The integration time

under these conditions can be calculated as follows:

Time = 0x7FFFFF × 4.83 μs = 40.5 sec

(22)

Reactive Energy Line Cycle Accumulation Mode

In reactive energy line cycle accumulation mode, the energy

accumulation of the ADE7953 is synchronized to the voltage

channel zero crossing so that the reactive energy on Current

Channel A and Current Channel B can be accumulated over

an integral number of half line cycles. Line cycle accumulation

mode is disabled by default and can be enabled on Current

Channel A and Current Channel B by setting the ALVAR and

BLVAR bits to 1 in the LCYCMODE register (Address 0x004).

The accumulation time should be written to the LINECYC

The number of half line cycles written to the LINECYC register

is used for both the Current Channel A and Current Channel B

accumulation periods. The ADE7953 can accumulate reactive

energy for up to 65,535 half line cycles. This equates to an accu-

mulation period of approximately 655 sec with 50 Hz inputs

and 546 sec with 60 Hz inputs.

At the end of a line cycle accumulation cycle, the RENERGYA and

RENERGYB registers are updated, and the CYCEND flag in the

IRQSTATA register (Address 0x22D and Address 0x32D) is set.

If the CYCEND bit in the IRQENA register is set, an external

interrupt is issued on the IRQ pin. In this way, the IRQ pin can

also be used to signal the completion of the line cycle accumula-

tion. Another accumulation cycle begins immediately as long as the

ALVAR and BLVAR bits in the LCYCMODE register remain set.

xVAROS

INTERNAL

ACCUMULATION

FIXED INTERNAL

THRESHOLD

CALIBRATION

CONTROL

ZERO-CROSSING

DETECTION

OUTPUT FROM

VOLTAGE CHANNEL

ADC

OUTPUT FROM

LPF2

RENERGYx

LINECYC

LPF1

xVARGAIN

Figure 52. Reactive Energy Line Cycle Accumulation

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