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PIC16LC771 数据表(PDF) 67 Page - Microchip Technology |
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PIC16LC771 数据表(HTML) 67 Page - Microchip Technology |
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67 / 224 page  1999-2013 Microchip Technology Inc. Advance Information DS41120C-page 67 PIC16C717/770/771 REGISTER 9-2: SYNC SERIAL PORT CONTROL REGISTER (SSPCON: 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit Master Mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave Mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit In SPI mode 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid setting over- flow. In Master mode, the overflow bit is not set since each new reception (and transmis- sion) is initiated by writing to the SSPBUF register. (Must be cleared in software). 0 = No overflow In I2C mode 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care" in Transmit mode. (Must be cleared in software). 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In both modes, when enabled, the I/O pins must be properly configured as input or output. In SPI mode 1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2C mode 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode 1 = IDLE state for clock is a high level 0 = IDLE state for clock is a low level In I2C Slave mode SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch) (used to ensure data setup time) In I2C Master mode Unused in this mode Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown |
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