PIC16LC771 datasheet(84/224 Pages) MICROCHIP

84 / 224 page

PIC16C717/770/771

DS41120C-page 84

Advance Information

 1999-2013 Microchip Technology Inc.

9.2.7

MULTI-MASTER OPERATION

In Multi-Master mode, the interrupt generation on the

detection of the START and STOP conditions allows

the determination of when the bus is free. The STOP

(P) and START (S) bits are cleared from a RESET or

when the MSSP module is disabled. Control of the I2C

bus may be taken when bit P (SSPSTAT<4>) is set, or

the bus is idle with both the S and P bits clear. When

the bus is busy, enabling the SSP Interrupt will gener-

ate the interrupt when the STOP condition occurs.

In multi-master operation, the SDA line must be moni-

tored for arbitration to see if the signal level is the

expected output level. This check is performed in hard-

ware, with the result placed in the BCLIF bit.

The states where arbitration can be lost are:

• Address Transfer

• Data Transfer

• A START Condition

• A Repeated START Condition

• An Acknowledge Condition

Refer to Application Note AN578, "Use of the SSP

Module in the I2C™ Multi-Master Environment."

9.2.8

I2C MASTER OPERATION

Master mode is enabled by setting and clearing the

appropriate SSPM bits in SSPCON and by setting the

SSPEN bit. Once Master mode is enabled, the user

has six options.

Assert a START condition on SDA and SCL.

Assert a Repeated START condition on SDA

and SCL.

Write to the SSPBUF register initiating transmis-

sion of data/address.

Generate a STOP condition on SDA and SCL.

Configure the I2C port to receive data.

Generate an Acknowledge condition at the end

of a received byte of data.

The master device generates all serial clock pulses and

the START and STOP conditions. A transfer is ended

with a STOP condition or with a Repeated START con-

dition. Since the Repeated START condition is also the

beginning of the next serial transfer, the I2C bus will not

be released.

9.2.9

BAUD RATE GENERATOR

The baud rate generator used for SPI mode operation

is used in the I2C Master mode to set the SCL clock fre-

quency. Standard SCL clock frequencies are 100 kHz,

400 kHz, and 1 MHz. One of these frequencies can be

achieved by setting the SSPADD register to the appro-

priate number for the selected Fosc frequency. One

half of the SCL period is equal to

[(SSPADD+1)

2]/Fosc.

The baud rate generator reload value is contained in

the lower seven bits of the SSPADD register (Figure 9-

14). When the BRG is loaded with this value, the BRG

counts down to 0 and stops until another reload occurs.

The BRG count is decremented twice per instruction

cycle (TCY) on the Q2 and Q4 clock.

In I2C Master mode, the BRG is reloaded automatically

provided that the SCL line is sampled high. For exam-

ple, if Clock Arbitration is taking place, the BRG reload

will be suppressed until the SCL line is released by the

slave allowing the pin to float high (Figure 9-15).

FIGURE 9-14:

BAUD RATE GENERATOR

BLOCK DIAGRAM

Note:

The MSSP Module, when configured in I2C

Master mode, does not allow queueing of

events. For instance, the user is not

allowed to initiate a START condition and

immediately write the SSPBUF register to

initiate transmission before the START

condition is complete. In this case, the

SSPBUF will not be written to, and the

WCOL bit will be set, indicating that a write

to the SSPBUF did not occur.

SSPM<3:0>

BRG Down Counter

BRG CLKOUT

Fosc/2

SSPADD<6:0>

SSPM<3:0>

SCL

Reload

Control

Reload

PIC16LC771 数据表(PDF) 84 Page - Microchip Technology

PIC16LC771 数据表(HTML) 84 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载