PIC16LC771 datasheet(87/224 Pages) MICROCHIP

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DS41120C-page 87

PIC16C717/770/771

9.2.12

I2C MASTER MODE

TRANSMISSION

In Master-transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The

first byte transmitted contains seven bits of address

data and the Read/Write (R/W) bit. In this case, the R/

W bit will be logic '0'. Subsequent serial data is trans-

mitted eight bits at a time. After each byte is transmit-

ted, an Acknowledge bit is received. START and STOP

conditions are output to indicate the beginning and the

end of a serial transfer.

Transmission of a data byte, a 7-bit address, or either

half of a 10-bit address is accomplished by simply writ-

ing a value to the SSPBUF register. This action will set

the buffer full flag (BF) and allow the baud rate genera-

tor to begin counting and start the next transmission.

Each bit of address/data will be shifted out onto the

SDA pin after the falling edge of SCL is asserted (see

data hold time spec). SCL is held low for one baud rate

generator roll over count (TBRG). Data should be valid

before SCL is released high (see data setup time

spec). When the SCL pin is released high, it is held that

way for TBRG, the data on the SDA pin must remain sta-

ble for that duration and some hold time after the next

falling edge of SCL. After the eighth bit is shifted out

(the falling edge of the eighth clock), the BF flag is

cleared and the master releases SDA. This allows the

slave device being addressed to respond with an ACK

bit during the ninth bit time. The status of ACK is read

into the ACKDT on the rising edge of the ninth clock. If

the master receives an Acknowledge, the Acknowl-

edge status bit (ACKSTAT) is cleared. Otherwise, the

bit is set. The SSPIF is set on the falling edge of the

ninth clock, and the master clock (baud rate generator)

is suspended until the next data byte is loaded into the

SSPBUF leaving SCL low and SDA unchanged

(Figure 9-18).

A typical transmit sequence would go as follows:

The user generates a START Condition by set-

ting the START enable bit (SEN) in SSPCON2.

SSPIF is set at the completion of the START

sequence.

The user resets the SSPIF bit and loads the

SSPBUF with seven bits of address plus R/W bit

to transmit.

Address and R/W is shifted out the SDA pin until

all eight bits are transmitted.

The MSSP Module shifts in the ACK bit from the

slave device, and writes its value into the

SSPCON2 register (SSPCON2<6>).

The module generates an interrupt at the end of

the ninth clock cycle by setting SSPIF.

The user resets the SSPIF bit and loads the

SSPBUF with eight bits of data.

DATA is shifted out the SDA pin until all eight bits

are transmitted.

The MSSP Module shifts in the ACK bit from the

slave device and writes its value into the

SSPCON2 register (SSPCON2<6>).

The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF

bit.

The user resets the SSPIF bit and generates a

STOP condition by setting the STOP enable bit

PEN in SSPCON2.

SSPIF is set when the STOP condition is complete.

9.2.12.1

BF STATUS FLAG

In Transmit mode, the BF bit (SSPSTAT<0>) is set

when the CPU writes to SSPBUF and is cleared when

all eight bits are shifted out.

9.2.12.2

WCOL STATUS FLAG

If the user writes the SSPBUF when a transmit is

already in progress (i.e. SSPSR is still shifting out a

data byte), then WCOL is set and the contents of the

buffer are unchanged (the write doesn’t occur).

WCOL must be cleared in software.

9.2.12.3

ACKSTAT STATUS FLAG

In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is

cleared when the slave has sent an Acknowledge

(ACK = 0), and is set when the slave does not Acknowl-

edge (ACK = 1). A slave sends an Acknowledge when

it has recognized its address (including a general call),

or when the slave has properly received its data.

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