PIC16LC771 datasheet(86/224 Pages) MICROCHIP

86 / 224 page

PIC16C717/770/771

DS41120C-page 86

Advance Information

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9.2.11

I2C MASTER MODE REPEATED

START CONDITION TIMING

A Repeated START condition occurs when the RSEN

bit (SSPCON2<1>) is set high while the I2C module is

in the idle state. When the RSEN bit is set, the SCL pin

is asserted low. When the SCL pin is sampled low, the

baud rate generator is loaded with the contents of

SSPADD<6:0> and begins counting. The SDA pin is

released (brought high) for one baud rate generator

count (TBRG). When the baud rate generator times out,

if SDA is sampled high, the SCL pin will be de-asserted

(brought high). When SCL is sampled high, the baud

rate generator is reloaded with the contents of

SSPADD<6:0> and begins counting. SDA and SCL

must be sampled high for one TBRG period. This action

is then followed by assertion of the SDA pin (SDA is

low) for one TBRG period while SCL is high. As soon as

a START condition is detected on the SDA and SCL

pins, the S bit (SSPSTAT<3>) will be set. Following

this, the baud rate generator is reloaded with the con-

tents of SSPAD<6:0> and begins counting. When the

BRG times out a third time, the RSEN bit in the

SSPCON2 register is automatically cleared and SCL is

pulled low. The SSPIF flag is set, which indicates the

Restart sequence is complete.

Immediately following the SSPIF bit transition to true,

the user may write the SSPBUF with the 7-bit address

in 7-bit mode, or the default first address in 10-bit

mode. After the first eight bits are transmitted and an

ACK is received, the user may then perform one of the

following:

• Transmit an additional eight bits of address (if the

user transmitted the first half of a 10-bit address

with R/W = 0),

• Transmit eight bits of data (if the user transmitted

a 7-bit address with R/W = 0), or

• Receive eight bits of data (if the user transmitted

either the first half of a 10-bit address or a 7-bit

address with R/W = 1).

9.2.11.1

WCOL STATUS FLAG

If the user writes the SSPBUF when a Repeated

START sequence is in progress, then WCOL is set and

the contents of the buffer are unchanged (the write

doesn’t occur).

FIGURE 9-17:

REPEAT START CONDITION WAVEFORM

Note 1: If RSEN is set while another event is in

progress, it will not take effect. Queuing of

events is not allowed.

2: A bus collision during the Repeated

START condition occurs if either of the

following is true:

SDA is sampled low when SCL

goes from low to high.

SCL goes low before SDA is

asserted low. This may indicate

that another master is attempting

to transmit a data “1”.

Note:

Because

queueing

events

not

allowed, writing of the lower five bits of

SSPCON2 is disabled until the Repeated

START condition is complete.

SDA

SCL

Sr = Repeated START

Write to SSPCON2

Write to SSPBUF occurs here.

Falling edge of ninth clock

End of Xmit

At completion of START bit,

hardware clears RSEN bit

1st Bit

Set S (SSPSTAT<3>)

TBRG

SDA = 1,

SCL (no change)

SCL = 1

occurs here.

TBRG

and sets SSPIF

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