PIC16LC771 datasheet(89/224 Pages) MICROCHIP

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Advance Information

DS41120C-page 89

PIC16C717/770/771

9.2.13

I2C MASTER MODE RECEPTION

In Master-receive mode, the first byte transmitted con-

tains seven bits of address data and the R/W bit. In this

case, the R/W bit will be logic '1'. Thus, the first byte

transmitted is a 7-bit slave address followed by a '1' to

indicate receive. Serial data is received via SDA, while

SCL outputs the serial clock. Serial data is received

eight bits at a time. After each byte is received, an

Acknowledge bit is transmitted. The START condition

indicates the beginning of a transmission. The master-

receiver terminates slave transmission by responding

to the last byte with a NACK Acknowledge and follows

this with a STOP condition to indicate to other masters

that the bus is free.

Master mode reception is enabled by setting the

receive enable bit, RCEN (SSPCON2<3>), immedi-

ately following the Acknowledge sequence.

The baud rate generator begins counting, and on each

rollover, the state of the SCL pin changes (high to low/

low to high) and data is shifted into the SSPSR. After

the falling edge of the eighth clock, the following events

occur:

• The receive enable bit is automatically cleared.

• The contents of the SSPSR are loaded into the

SSPBUF.

• The BF flag is set.

• The SSPIF is set.

• The baud rate generator is suspended from

counting, holding SCL low.

The SSP is now in IDLE state, awaiting the next com-

mand. When the buffer is read by the CPU, the BF flag

is automatically cleared. The user can then send an

Acknowledge bit at the end of reception by clearing the

ACKDT bit (SSPCON2<5>) and setting the Acknowl-

edge sequence enable bit, ACKEN (SSPCON2<4>).

A typical receive sequence would go as follows:

The user generates a START Condition by set-

ting the START enable bit (SEN) in SSPCON2.

SSPIF is set at the completion of the START

sequence.

The user resets the SSPIF bit and loads the

SSPBUF with seven bits of address in the MSbs

and the LSb (R/W bit) set to '1' for receive.

Address and R/W is shifted out the SDA pin until

all eight bits are transmitted.

The MSSP Module shifts in the ACK bit from the

slave device, and writes its value into the

SSPCON2 register (SSPCON2<6>).

The module generates an interrupt at the end of

the ninth clock cycle by setting SSPIF.

The user resets the SSPIF bit and sets the

RCEN bit to enable reception.

DATA is shifted into the SDA pin until all eight

bits are received.

The MSSP module sets the SSPIF bit and clears

the RCEN bit at the falling edge of the eighth

clock.

The user resets the SSPIF bit and sets the

ACKDT bit to '0' (ACK), if another byte is antici-

pated. Otherwise, the ACKDT bit is set to '1'

(NACK) to terminate reception. The user sets

ADKEN to start the Acknowledge sequence.

The MSSP module sets the SSPIF bit at the

completion of the Acknowledge.

If a NACK was sent in step ( j), then the user pro-

ceeds with step ( m). Otherwise, reception con-

tinues by repeating steps ( g) through ( j).

m) The user generates a STOP condition by setting

the STOP enable bit PEN in SSPCON2.

SSPIF is set when the STOP condition is complete.

9.2.13.1

BF STATUS FLAG

In receive operation, BF is set when an address or data

byte is loaded into SSPBUF from SSPSR. It is cleared

by hardware when SSPBUF is read.

9.2.13.2

SSPOV STATUS FLAG

In receive operation, SSPOV is set when eight bits are

received into the SSPSR and the BF flag is already set

from a previous reception.

9.2.13.3

WCOL STATUS FLAG

If the user writes the SSPBUF when a receive is

already in progress (i.e., SSPSR is still shifting in a data

byte), then WCOL is set and the contents of the buffer

are unchanged (the write doesn’t occur).

Note:

The MSSP Module must be in an IDLE

STATE before the RCEN bit is set or the

RCEN bit will be disregarded.

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