PIC16LC771 datasheet(80/224 Pages) MICROCHIP

80 / 224 page

PIC16C717/770/771

DS41120C-page 80

Advance Information

 1999-2013 Microchip Technology Inc.

9.2.2.4

SLAVE TRANSMISSION

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the SSP-

STAT register is set. The received address is loaded

into the SSPBUF register on the falling edge of the

eighth SCL pulse. The ACK pulse will be sent on the

ninth bit, and the SCL pin is held low. The slave module

automatically stretches the clock by holding the SCL

line low so that the master will be unable to assert

another clock pulse until the slave is finished preparing

the transmit data. The transmit data must be loaded

into the SSPBUF register, which also loads the SSPSR

to release the SCL pin from the forced low condition.

The eight data bits are shifted out on the falling edges

of the SCL input. This ensures that the SDA signal is

valid during the SCL high time (Figure 9-10).

The ACK or NACK signal from the master-receiver is

latched on the rising edge of the ninth SCL input pulse.

The master-receiver terminates slave transmission by

sending a NACK. If the SDA line is high (NACK), then

the data transfer is complete. When the NACK is

latched by the slave, the slave logic is RESET which

also resets the R/W bit to '0'. The slave module then

monitors for another occurrence of the START bit. The

slave firmware knows not to load another byte into the

SSPBUF register by sensing that the buffer is empty

(BF = 0) and the R/W bit has gone low. If the SDA line

is low (ACK), the R/W bit remains high indicating that

the next transmit data must be loaded into the SSPBUF

An MSSP interrupt (SSPIF flag) is generated for each

data transfer byte on the falling edge of the ninth clock

pulse. The SSPIF flag bit must be cleared in software.

The SSPSTAT register is used to determine the status

of the byte transfer.

For more information about the I2C Slave mode, refer

to Application Note AN734, “Using the PIC® SSP for

Slave I2C™ Communication”.

FIGURE 9-10:

I2C SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

SDA

SCL

SSPIF

BF (SSPSTAT<0>)

CKP (SSPCON<4>)

ACK

NACK

Transmitting Data

R/W = 1

Receiving Address

567

cleared in software

SSPBUF is written in software

From SSP interrupt

service routine

Set bit after writing to SSPBUF

Data in

sampled

SCL held low

until SSPBUF

is written

(the SSPBUF must be written-to

before the CKP bit can be set)

R/W

 0

Master terminates transmission

by responding with NACK

PIC16LC771 数据表(PDF) 80 Page - Microchip Technology

PIC16LC771 数据表(HTML) 80 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载