PIC16LC771 datasheet(73/224 Pages) MICROCHIP

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Advance Information

DS41120C-page 73

PIC16C717/770/771

9.1.5

SLAVE MODE

In Slave mode, the data is transmitted and received as

the external clock pulses appear on SCK. When the

last bit is latched the interrupt flag bit SSPIF (PIR1<3>)

is set.

While in Slave mode, the external clock is supplied by

the external clock source on the SCK pin. This external

clock must meet the minimum high and low times as

specified in the electrical specifications.

While in SLEEP mode, the slave can transmit/receive

data. When a byte is received, the device will wake-up

from SLEEP.

9.1.6

SLAVE SELECT

SYNCHRONIZATION

The SS pin allows a Synchronous Slave mode. The

SPI must be in Slave mode with SS pin control

enabled (SSPCON<3:0> = 0100). The pin must not

be driven low for the SS pin to function as an input.

TRISB<1> must be set. When the SS pin is low,

transmission and reception are enabled and the

SDO pin is driven. When the SS pin goes high, the

SDO pin is no longer driven, even if in the middle of

a transmitted byte, and becomes a floating output.

External pull-up/ pull-down resistors may be desir-

able, depending on the application.

When the SPI module RESETS, the bit counter is

forced to 0. This can be done by either forcing the SS

pin to a high level or clearing the SSPEN bit.

To emulate two-wire communication, the SDO pin can

be connected to the SDI pin. When the SPI needs to

operate as a receiver, the SDO pin can be configured

as an input. This disables transmissions from the SDO.

The SDI can always be left as an input (SDI function)

since it cannot create a bus conflict.

FIGURE 9-4:

SLAVE SYNCHRONIZATION WAVEFORM

Note 1: When the SPI module is in Slave mode

with SS pin control enabled, (SSP-

CON<3:0> = 0100) the SPI module will

RESET if the SS pin is set to VDD.

2: If the SPI is used in Slave Mode with

CKE = '1', then SS pin control must be

enabled.

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI

bit7

SDO

bit7

bit6

bit7

SSPIF

Interrupt

(SMP = 0)

CKE = 0)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

Flag

bit0

bit7

bit0

Next Q4 cycle

after Q2



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