LCMXO2-256ZE-3UMG64C datasheet(33/106 Pages) LATTICE

33 / 106 page

2-29

Architecture

MachXO2 Family Data Sheet

Figure 2-21. I

2C Core Block Diagram

Table 2-15 describes the signals interfacing with the I

2C cores.

Table 2-15. I

2C Core Signal Description

Hardened SPI IP Core

Every MachXO2 device has a hard SPI IP core that can be configured as a SPI master or slave. When the IP core

is configured as a master it will be able to control other SPI enabled chips connected to the SPI bus. When the core

is configured as the slave, the device will be able to interface to an external SPI master. The SPI IP core on

MachXO2 devices supports the following functions:

• Configurable Master and Slave modes

• Full-Duplex data transfer

• Mode fault error flag with CPU interrupt capability

• Double-buffered data register

• Serial clock with programmable polarity and phase

• LSB First or MSB First Data Transfer

• Interface to custom logic through 8-bit WISHBONE interface

Signal Name

I/O

Description

i2c_scl

Bi-directional

Bi-directional clock line of the I

2C core. The signal is an output if the I2C core is in master

mode. The signal is an input if the I

2C core is in slave mode. MUST be routed directly to the

pre-assigned I/O of the chip. Refer to the Pinout Information section of this document for

detailed pad and pin locations of I

2C ports in each MachXO2 device.

i2c_sda

Bi-directional

Bi-directional data line of the I

2C core. The signal is an output when data is transmitted from

the I

2C core. The signal is an input when data is received into the I2C core. MUST be routed

directly to the pre-assigned I/O of the chip. Refer to the Pinout Information section of this

document for detailed pad and pin locations of I

2C ports in each MachXO2 device.

i2c_irqo

Output

Interrupt request output signal of the I

2C core. The intended usage of this signal is for it to be

connected to the WISHBONE master controller (i.e. a microcontroller or state machine) and

request an interrupt when a specific condition is met. These conditions are described with

the I

2C register definitions.

cfg_wake

Output

Wake-up signal – To be connected only to the power module of the MachXO2 device. The

signal is enabled only if the “Wakeup Enable” feature has been set within the EFB GUI, I

Tab.

cfg_stdby

Output

Stand-by signal – To be connected only to the power module of the MachXO2 device. The

signal is enabled only if the “Wakeup Enable” feature has been set within the EFB GUI, I

Tab.

EFB

SCL

SDA

Configuration

Logic

Core

Logic/

Routing

Power

Control

I2C

Registers

EFB

WISHBONE

Interface

Control

Logic

I2C Function

LCMXO2-256ZE-3UMG64C 数据表(PDF) 33 Page - Lattice Semiconductor

LCMXO2-256ZE-3UMG64C 数据表(HTML) 33 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

LCMXO2-256ZE-3UMG64C 数据表(PDF) 33 Page - Lattice Semiconductor

LCMXO2-256ZE-3UMG64C 数据表(HTML) 33 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载