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LCMXO2-256ZE-3UMG64C 数据表(PDF) 65 Page - Lattice Semiconductor |
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LCMXO2-256ZE-3UMG64C 数据表(HTML) 65 Page - Lattice Semiconductor |
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65 / 106 page  3-26 DC and Switching Characteristics MachXO2 Family Data Sheet Generic DDR4 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_RX.ECLK.Centered 9 tSU Input Data Setup Before ECLK MachXO2-640U, MachXO2-1200/U and larger devices, bottom side only 0.434 — 0.535 — 0.630 — ns tHO Input Data Hold After ECLK 0.385 — 0.395 — 0.463 — ns fDATA DDRX4 Serial Input Data Speed —420 —352 —292 Mbps fDDRX4 DDRX4 ECLK Frequency — 210 — 176 — 146 MHz fSCLK SCLK Frequency — 53 — 44 — 37 MHz 7:1 LVDS Inputs – GDDR71_RX.ECLK.7.1 9 tDVA Input Data Valid After ECLK MachXO2-640U, MachXO2-1200/U and larger devices, bottom side only — 0.307 — 0.316 — 0.326 UI tDVE Input Data Hold After ECLK 0.662 — 0.650 — 0.649 — UI fDATA DDR71 Serial Input Data Speed —420 —352 —292 Mbps fDDR71 DDR71 ECLK Frequency — 210 — 176 — 146 MHz fCLKIN 7:1 Input Clock Frequency (SCLK) (minimum limited by PLL) —60—50 —42 MHz Generic DDR Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Aligned 9 tDIA Output Data Invalid After CLK Output All MachXO2 devices, all sides — 0.850 — 0.910 — 0.970 ns tDIB Output Data Invalid Before CLK Output — 0.850 — 0.910 — 0.970 ns fDATA DDRX1 Output Data Speed — 140 — 116 — 98 Mbps fDDRX1 DDRX1 SCLK frequency — 70 — 58 — 49 MHz Generic DDR Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_TX.SCLK.Centered 9 tDVB Output Data Valid Before CLK Output All MachXO2 devices, all sides 2.720 — 3.380 — 4.140 — ns tDVA Output Data Valid After CLK Output 2.720 — 3.380 — 4.140 — ns fDATA DDRX1 Output Data Speed — 140 — 116 — 98 Mbps fDDRX1 DDRX1 SCLK Frequency (minimum limited by PLL) —70—58 —49 MHz Generic DDRX2 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Aligned 9 tDIA Output Data Invalid After CLK Output MachXO2-640U, MachXO2-1200/U and larger devices, top side only — 0.270 — 0.300 — 0.330 ns tDIB Output Data Invalid Before CLK Output — 0.270 — 0.300 — 0.330 ns fDATA DDRX2 Serial Output Data Speed —280 —234 —194 Mbps fDDRX2 DDRX2 ECLK frequency — 140 — 117 — 97 MHz fSCLK SCLK Frequency — 70 — 59 — 49 MHz Parameter Description Device -3 -2 -1 Units Min. Max. Min. Max. Min. Max. |
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