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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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LCMXO2-256ZE-3UMG64C 数据表(PDF) 23 Page - Lattice Semiconductor |
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LCMXO2-256ZE-3UMG64C 数据表(HTML) 23 Page - Lattice Semiconductor |
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23 / 106 page  2-19 Architecture MachXO2 Family Data Sheet These gearboxes have three stage pipeline registers. The first stage registers sample the high-speed input data by the high-speed edge clock on its rising and falling edges. The second stage registers perform data alignment based on the control signals UPDATE and SEL0 from the control block. The third stage pipeline registers pass the data to the device core synchronized to the low-speed system clock. Figure 2-16 shows a block diagram of the input gearbox. Figure 2-16. Input Gearbox D Q D ECLK0/1 SCLK Q21 Q0_ S2 S0 D Q D Q T2 T0 Q0 Q2 D Q D Q CE D Q CE D Q Q65 Q43 S6 S4 D Q D Q T6 T4 D Q cdn D Q CE D Q cdn CE D Q Q54 Q_6 S3 S5 D D T3 T5 Q6 D Q D Q CE D Q CE D Q Q10 Q32 S1 D T1 D Q D Q CE Q65 Q65 Q43 Q43 Q21 Q10 Q21 Q32 Q54 Q_6 Q54 Q32 SEL0 Q4 Q5 Q1 Q3 S7 D Q T7 D Q CE Q7 UPDATE Q_6 |
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