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LCMXO2-256ZE-3UMG64C 数据表(PDF) 15 Page - Lattice Semiconductor |
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LCMXO2-256ZE-3UMG64C 数据表(HTML) 15 Page - Lattice Semiconductor |
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15 / 106 page  2-11 Architecture MachXO2 Family Data Sheet Figure 2-8. sysMEM Memory Primitives Table 2-6. EBR Signal Descriptions Port Name Description Active State CLK Clock Rising Clock Edge CE Clock Enable Active High OCE 1 Output Clock Enable Active High RST Reset Active High BE 1 Byte Enable Active High WE Write Enable Active High AD Address Bus — DI Data In — DO Data Out — CS Chip Select Active High AFF FIFO RAM Almost Full Flag — FF FIFO RAM Full Flag — AEF FIFO RAM Almost Empty Flag — EF FIFO RAM Empty Flag — RPRST FIFO RAM Read Pointer Reset — 1. Optional signals. 2. For dual port EBR primitives a trailing ‘A’ or ‘B’ in the signal name specifies the EBR port A or port B respectively. 3. For FIFO RAM mode primitive, a trailing ‘R’ or ‘W’ in the signal name specifies the FIFO read port or write port respec- tively. 4. For FIFO RAM mode primitive FULLI has the same function as CSW(2) and EMPTYI has the same function as CSR(2). 5. In FIFO mode, CLKW is the write port clock, CSW is the write port chip select, CLKR is the read port clock, CSR is the read port chip select, ORE is the output read enable. DI[17:0] CLKW WE FIFO RAM DO[17:0] RST FULLI AFF FF AEF EF CLKR RE CSR[1:0] ORE RPRST CSW[1:0] EMPTYI ROM DO[17:0] AD[12:0] CLK CE RST CS[2:0] OCE EBR EBR AD[12:0] DI[8:0] DO[8:0] CLK CE RST WE CS[2:0] OCE Single-Port RAM ADA[12:0] DIA[8:0] CLKA CEA RSTA WEA CSA[2:0] DOA[8:0] OCEA ADB[12:0] DI[8:0] CLKB CEB RSTB WEB CSB[2:0] DOB[8:0] OCEB True Dual Port RAM ADW[8:0] DI[17:0] CLKW CEW RST CSW[2:0] ADR[12:0] CLKR CER DO[17:0] CSR[2:0] OCER BE[1:0] Pseudo Dual Port RAM EBR EBR EBR |
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