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LCMXO2-256ZE-3UMG64C 数据表(PDF) 58 Page - Lattice Semiconductor |
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LCMXO2-256ZE-3UMG64C 数据表(HTML) 58 Page - Lattice Semiconductor |
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58 / 106 page  3-19 DC and Switching Characteristics MachXO2 Family Data Sheet tHPLL Clock to Data Hold - PIO Input Register MachXO2-1200HC-HE 0.41 — 0.48 — 0.55 — ns MachXO2-2000HC-HE 0.42 — 0.49 — 0.56 — ns MachXO2-4000HC-HE 0.43 — 0.50 — 0.58 — ns MachXO2-7000HC-HE 0.46 — 0.54 — 0.62 — ns tSU_DELPLL Clock to Data Setup - PIO Input Register with Data Input Delay MachXO2-1200HC-HE 2.88 — 3.19 — 3.72 — ns MachXO2-2000HC-HE 2.87 — 3.18 — 3.70 — ns MachXO2-4000HC-HE 2.96 — 3.28 — 3.81 — ns MachXO2-7000HC-HE 3.05 — 3.35 — 3.87 — ns tH_DELPLL Clock to Data Hold - PIO Input Register with Input Data Delay MachXO2-1200HC-HE -0.83 — -0.83 — -0.83 — ns MachXO2-2000HC-HE -0.83 — -0.83 — -0.83 — ns MachXO2-4000HC-HE -0.87 — -0.87 — -0.87 — ns MachXO2-7000HC-HE -0.91 — -0.91 — -0.91 — ns Generic DDRX1 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Aligned 9 tDVA Input Data Valid After CLK All MachXO2 devices, all sides — 0.317 — 0.344 — 0.368 UI tDVE Input Data Hold After CLK 0.742 — 0.702 — 0.668 — UI fDATA DDRX1 Input Data Speed — 300 — 250 — 208 Mbps fDDRX1 DDRX1 SCLK Frequency — 150 — 125 — 104 MHz Generic DDRX1 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX1_RX.SCLK.Centered 9 tSU Input Data Setup Before CLK All MachXO2 devices, all sides 0.566 — 0.560 — 0.538 — ns tHO Input Data Hold After CLK 0.778 — 0.879 — 1.090 — ns fDATA DDRX1 Input Data Speed — 300 — 250 — 208 Mbps fDDRX1 DDRX1 SCLK Frequency — 150 — 125 — 104 MHz Generic DDRX2 Inputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Aligned 9 tDVA Input Data Valid After CLK MachXO2-640U, MachXO2-1200/U and larger devices, bottom side only — 0.316 — 0.342 — 0.364 UI tDVE Input Data Hold After CLK 0.710 — 0.675 — 0.679 — UI fDATA DDRX2 Serial Input Data Speed — 664 — 554 — 462 Mbps fDDRX2 DDRX2 ECLK Frequency — 332 — 277 — 231 MHz fSCLK SCLK Frequency — 166 — 139 — 116 MHz Generic DDRX2 Inputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_RX.ECLK.Centered 9 tSU Input Data Setup Before CLK MachXO2-640U, MachXO2-1200/U and larger devices, bottom side only 0.233 — 0.219 — 0.198 — ns tHO Input Data Hold After CLK 0.287 — 0.287 — 0.344 — ns fDATA DDRX2 Serial Input Data Speed — 664 — 554 — 462 Mbps fDDRX2 DDRX2 ECLK Frequency — 332 — 277 — 231 MHz fSCLK SCLK Frequency — 166 — 139 — 116 MHz Parameter Description Device -6 -5 -4 Units Min. Max. Min. Max. Min. Max. |
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