LCMXO2-256ZE-3UMG64C datasheet(36/106 Pages) LATTICE

36 / 106 page

2-32

Architecture

MachXO2 Family Data Sheet

User Flash Memory (UFM)

MachXO2-640/U and higher density devices provide a User Flash Memory block, which can be used for a variety of

applications including storing a portion of the configuration image, initializing EBRs, to store PROM data or, as a

general purpose user Flash memory. The UFM block connects to the device core through the embedded function

block WISHBONE interface. Users can also access the UFM block through the JTAG, I

2C and SPI interfaces of the

device. The UFM block offers the following features:

• Non-volatile storage up to 256Kbits

• 100K write cycles

• Write access is performed page-wise; each page has 128 bits (16 bytes)

• Auto-increment addressing

• WISHBONE interface

For more information on the UFM, please refer to TN1205, Using User Flash Memory and Hardened Control Func-

tions in MachXO2 Devices.

Standby Mode and Power Saving Options

MachXO2 devices are available in three options for maximum flexibility: ZE, HC and HE devices. The ZE devices

have ultra low static and dynamic power consumption. These devices use a 1.2V core voltage that further reduces

power consumption. The HC and HE devices are designed to provide high performance. The HC devices have a

built-in voltage regulator to allow for 2.5V VCC and 3.3V VCC while the HE devices operate at 1.2V VCC.

MachXO2 devices have been designed with features that allow users to meet the static and dynamic power

requirements of their applications by controlling various device subsystems such as the bandgap, power-on-reset

circuitry, I/O bank controllers, power guard, on-chip oscillator, PLLs, etc. In order to maximize power savings,

MachXO2 devices support an ultra low power Stand-by mode. While most of these features are available in all

three device types, these features are mainly intended for use with MachXO2 ZE devices to manage power con-

sumption.

In the stand-by mode the MachXO2 devices are powered on and configured. Internal logic, I/Os and memories are

switched on and remain operational, as the user logic waits for an external input. The device enters this mode

when the standby input of the standby controller is toggled or when an appropriate I

2C or JTAG instruction is issued

by an external master. Various subsystems in the device such as the band gap, power-on-reset circuitry etc can be

configured such that they are automatically turned “off” or go into a low power consumption state to save power

when the device enters this state.

LCMXO2-256ZE-3UMG64C 数据表(PDF) 36 Page - Lattice Semiconductor

LCMXO2-256ZE-3UMG64C 数据表(HTML) 36 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载