ADP5063

Data Sheet

Rev. 0 | Page 6 of 44

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

LOGIC INPUT PINS

Maximum Voltage on Digital Inputs

5.5

V

Applies to SCL, SDA, DIG_IO1, DIG_IO2, DIG_IO3

Maximum Logic Low Input Voltage

0.5

V

Applies to SCL, SDA, DIG_IO1, DIG_IO2, DIG_IO3

Minimum Logic High Input Voltage

1.2

V

Applies to SCL, SDA, DIG_IO1, DIG_IO2, DIG_IO3

Pull-Down Resistance

215

350

610

kΩ

Applies to DIG_IO1, DIG_IO2, DIG_IO3

1

Undervoltage lockout generated normally from ISO_Sx or ISO_Bx; in certain transition cases, it can be generated from VINx.

2

3

The output current during charging may be limited by the input current limit or by the isothermal charging mode.

4

During weak charging mode, the charger provides at least 20 mA of charging current via the trickle charge branch to the battery unless trickle charging is disabled.

Any residual current that is not required by the system is also used to charge the battery.

5

RECOMMENDED INPUT AND OUTPUT CAPACITANCES

Table 2.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

CAPACITANCES

Effective capacitance

VINx

4

10

μF

CBP

60

100

140

nF

ISO_Sx

10

22

100

μF

ISO_Bx

10

22

μF

Table 3.

Parameter1

Symbol

Min

Typ

Max

Unit

Capacitive Load for Each Bus Line

400

pF

SCL Clock Frequency

400

kHz

SCL High Time

0.6

µs

SCL Low Time

1.3

µs

Data Setup Time

100

ns

Data Hold Time

0

0.9

µs

Setup Time for Repeated Start

0.6

µs

Hold Time for Start/Repeated Start

0.6

µs

Bus Free Time Between a Stop and a Start Condition

1.3

µs

Setup Time for Stop Condition

0.6

µs

Rise Time of SCL/SDA

20

300

ns

Fall Time of SCL/SDA

20

300

ns

Pulse Width of Suppressed Spike

0

50

ns

1

Guaranteed by design.

2

A master device must provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL (see Figure 2).