33FJ128GP708 datasheet(21/90 Pages) MICROCHIP

21 / 90 page

Preliminary

DS70155C-page 19

dsPIC33F

6.0

SYSTEM INTEGRATION

System

management

services

provided

the

dsPIC33F device family include:

• Control of clock options and oscillators

• Power-on Reset

• Oscillator Start-up Timer/Stabilizer

• Watchdog Timer with RC oscillator

• Fail-Safe Clock Monitor

• Reset by multiple sources

6.1

Clock Options and Oscillators

There are 7 clock options provided by the dsPIC33F:

• FRC Oscillator

• FRC Oscillator with PLL

• Primary (XT, HS or EC) Oscillator

• Primary Oscillator with PLL

• Secondary (LP) Oscillator

• LPRC Oscillator

The FRC (Fast RC) internal oscillator runs at a nominal

frequency of 7.37 MHz. The user software can tune the

FRC frequency. User software can specify a factor by

which this clock frequency is scaled.

The primary oscillator can use one of the following as

its clock source:

XT (Crystal): Crystals and ceramic resonators in

the range of 3 MHz to 10 MHz. The crystal is

connected to the OSC1 and OSC2 pins.

HS (High-Speed Crystal): Crystals in the range

of 10 MHz to 40 MHz. The crystal is connected

to the OSC1 and OSC2 pins.

EC (External Clock): External clock signal in the

range of 0.8 MHz to 64 MHz. The external clock

signal is directly applied to the OSC1 pin.

The secondary (LP) oscillator is designed for low power

and uses a 32 kHz crystal or ceramic resonator. The LP

oscillator uses the SOSCI and SOSCO pins.

The LPRC (Low-Power RC) internal oscIllator runs at a

nominal frequency of 32.768 kHz. Another scaled

reference clock is used by the Watchdog Timer (WDT)

and Fail-Safe Clock Monitor (FSCM).

The clock signals generated by the FRC and primary

oscillators can be optionally applied to an on-chip

Phase Locked Loop (PLL) to provide a wide range of

output frequencies for device operation. The input to

the PLL can be in the range of 1.6 MHz to 16 MHz, and

the PLL Phase Detector Input Divider, PLL Multiplier

Ratio and PLL Voltage Controlled Oscillator (VCO) can

be individually configured by user software to generate

output frequencies in the range of 25 MHz to 160 MHz.

The output of the oscillator (or the output of the PLL if

a PLL mode has been selected) is divided by 4 to

generate the device instruction clock (FCY). FCY

defines the operating speed of the device, and speeds

up to 40 MHz are supported by the dsPIC33F

architecture.

The dsPIC33F oscillator system provides:

• Various external and internal oscillator options as

clock sources

• An on-chip PLL to scale the internal operating

frequency to the required system clock frequency

• The internal FRC oscillator can also be used with

the PLL, thereby allowing full-speed operation

without any external clock generation hardware

• Clock switching between various clock sources

• Programmable clock postscaler for system power

savings

• A Fail-Safe Clock Monitor (FSCM) that detects

clock failure and takes fail-safe measures

• A Clock Control register (OSCCON)

• Nonvolatile configuration bits for main oscillator

selection.

A simplified block diagram of the oscillator system is

shown in Figure 6-1.

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