33FJ128GP708 datasheet(34/90 Pages) MICROCHIP

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dsPIC33F

DS70155C-page 32

Preliminary

9.0

dsPIC33F INSTRUCTION SET

9.1

Introduction

The dsPIC33F instruction set provides a broad suite of

instructions which supports traditional microcontroller

applications, and a class of instructions which supports

math-intensive applications. Since almost all of the

functionality of the PICmicro® MCU instruction set has

been maintained, this hybrid instruction set allows a

friendly DSP migration path for users already familiar

with the PICmicro microcontroller.

9.2

Instruction Set Overview

The dsPIC33F instruction set contains 84 instructions

which can be grouped into the ten functional categories

shown in Table 9-1. Table 9-2 defines the symbols

used in the instruction summary tables, Table 9-3

through Table 9-12. These tables define the syntax,

description,

storage

and

execution

requirements

for each instruction. Storage requirements are repre-

sented in 24-bit instruction words and execution

requirements are represented in instruction cycles.

Most instructions have several different addressing

modes and execution flows which require different

instruction variants. For instance, there are six unique

ADD

instructions and each instruction variant has its

own instruction encoding.

TABLE 9-1:

dsPIC33F INSTRUCTION

GROUPS

9.2.1

MULTI-CYCLE INSTRUCTIONS

As the instruction summary tables show, most

instructions execute in a single cycle with the following

exceptions:

• Instructions DO, MOV.D, POP.D, PUSH.D,

TBLRDH, TBLRDL, TBLWTH

and TBLWTL

require 2 cycles to execute.

• Instructions DIVF, DIV.S, DIV.U are single-

cycle instructions, which should be executed

18 consecutive times as the target REPEAT

instruction.

• Instructions that change the program counter also

require 2 cycles to execute, with the extra cycle

executed as a NOP. Skip instructions, which skip

over a 2-word instruction, require 3 instruction

cycles to execute with 2 cycles executed as a

NOP

•The RETFIE, RETLW and RETURN are special

cases of instructions that change the program

counter. These execute in 3 cycles unless an

exception is pending, and then they execute in

2 cycles.

9.2.2

MULTI-WORD INSTRUCTIONS

As the instruction summary tables show, almost all

instructions consume one instruction word (24 bits),

with the exception of the CALL, DO and GOTO

instructions, which are flow instructions listed in

Table 9-9. These instructions require two words of

memory because their opcodes embed large literal

operands.

Functional Group

Summary Table

Move Instructions

Table 9-3

Math Instructions

Table 9-4

Logic Instructions

Table 9-5

Rotate/Shift Instructions

Table 9-6

Bit Instructions

Table 9-7

Compare/Skip Instructions

Table 9-8

Program Flow Instructions

Table 9-9

Shadow/Stack Instructions

Table 9-10

Control Instructions

Table 9-11

DSP Instructions

Table 9-12

Note:

Instructions that access program memory

as data, using Program Space Visibility,

incur some cycle count overhead.

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