33FJ128GP708 datasheet(13/90 Pages) MICROCHIP

13 / 90 page

Preliminary

DS70155C-page 11

dsPIC33F

3.3

Data Address Space

The core has two data spaces, X and Y. These data

spaces can be considered either separate (for some

DSP instructions), or as one unified linear address

range (for MCU instructions). The data spaces are

accessed using two Address Generation Units (AGUs)

and separate data paths. This feature allows certain

instructions to concurrently fetch two words from RAM,

thereby enabling efficient execution of DSP algorithms

such as Finite Impulse Response (FIR) filtering and

Fast Fourier Transform (FFT).

3.3.1

X AND Y DATA SPACES

The X data space is used by all instructions and

supports all addressing modes. There are separate

read and write data buses for X data space. The X read

data bus is the read data path for all instructions that

view data space as combined X and Y address space.

It is also the X data prefetch path for the dual operand

DSP instructions (MAC class).

The Y data space is used in concert with the X data

space by the MAC class of instructions (CLR, ED,

EDAC, MAC, MOVSAC, MPY, MPY.N

and MSC) to

provide two concurrent data read paths.

Both the X and Y data spaces support Modulo

Addressing for all instructions, subject to addressing

mode restrictions. Bit-Reversed Addressing is only

supported for writes to X data space.

All data memory writes, including in DSP instructions,

view data space as combined X and Y address space.

The boundary between the X and Y data spaces is

device-dependent (an example is shown in Figure 3-3)

and is not user-programmable.

All effective addresses are 16 bits wide and point to

bytes within the data space. Therefore, the data space

address range is 64 Kbytes or 32K words, though the

implemented memory locations vary from one device to

another.

3.3.2

DMA RAM

Every dsPIC33F device contains 2 Kbytes of DMA RAM

located at the end of Y data space. Memory locations in

the DMA RAM space are accessible simultaneously by

the CPU and the DMA Controller module. DMA RAM is

utilized by the DMA Controller to store data to be

transferred to various peripherals using DMA, as well as

data transferred from various peripherals using DMA.

When the CPU and the DMA Controller attempt to

concurrently write to the same DMA RAM location, the

hardware ensures that the CPU is given precedence in

accessing the DMA RAM location. Therefore, the DMA

RAM provides a reliable means of transferring DMA

data without ever having to stall the CPU.

3.3.3

DATA SPACE WIDTH

The core data width is 16 bits. All internal registers are

organized as 16-bit wide words. Data space memory is

organized in byte addressable, 16-bit wide blocks.

Figure 3-3 depicts a sample data space memory map

for the dsPIC33F device with 33 Kbytes of RAM.

3.3.4

DATA ALIGNMENT

help

maintain

backward

compatibility

with

PICmicro® devices and improve data space memory

usage efficiency, the dsPIC33F instruction set supports

both word and byte operations. Data is aligned in data

memory and registers as words, but all data space EAs

resolve to bytes. Data byte reads will read the complete

word which contains the byte, using the Least

Significant bit (LSb) of any EA to determine which byte

to select.

As a consequence of this byte accessibility, all effective

address

calculations

are

internally

scaled.

For

example, the core would recognize that Post-Modified

in a value of Ws + 1 for byte operations and Ws + 2 for

word operations.

All word accesses must be aligned to an even address.

Misaligned word data fetches are not supported.

Should a misaligned read or write be attempted, a trap

will then be executed, allowing the system and/or user

to examine the machine state prior to execution of the

address Fault.

33FJ128GP708 数据表(PDF) 13 Page - Microchip Technology

33FJ128GP708 数据表(HTML) 13 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

数据表下载