33FJ128GP708 datasheet(17/90 Pages) MICROCHIP

17 / 90 page

Preliminary

DS70155C-page 15

dsPIC33F

4.0

DIRECT MEMORY ACCESS

Direct Memory Access (DMA) is a very efficient

mechanism of copying data between peripheral SFRs

(e.g., UART Receive register, Input Capture 1 buffer)

and buffers or variables stored in RAM with minimal

CPU

intervention.

The

DMA

Controller

can

automatically copy entire blocks of data, without the

user software having to read or write peripheral Special

Function Registers (SFRs) every time a peripheral

interrupt occurs. To exploit the DMA capability, the

corresponding user buffers or variables must be

located in DMA RAM space.

The DMA Controller features eight identical data

transfer channels, each with its own set of control and

status registers. The UART, SPI, DCI, Input Capture,

Output Compare, ECAN™ and A/D modules can utilize

DMA. Each DMA channel can be configured to copy

data either from buffers stored in DMA RAM to

peripheral SFRs or from peripheral SFRs to buffers in

DMA RAM.

Each channel supports the following features:

• Word or byte-sized data transfers

• Transfers from peripheral to DMA RAM or DMA

RAM to peripheral

• Indirect addressing of DMA RAM locations with or

without automatic post-increment

• Peripheral Indirect Addressing – In some

peripherals, the DMA RAM read/write addresses

may be partially derived from the peripheral

• One-Shot Block Transfers – Terminating DMA

transfer after one block transfer

• Continuous Block Transfers – Reloading DMA

RAM buffer start address after every block

transfer is complete

• Ping-Pong Mode – Switching between two DMA

RAM start addresses between successive block

transfers, thereby filling two buffers alternately

• Automatic or manual initiation of block transfers

• Each channel can select from 32 possible

sources of data sources or destinations

For each DMA channel, a DMA interrupt request is

generated

when

block

transfer

complete.

Alternatively, an interrupt can be generated when half of

the block has been filled. Additionally, a DMA error trap

is generated in either of the following Fault conditions:

• DMA RAM data write collision between the CPU

and a peripheral

• Peripheral SFR data write collision between the

CPU and the DMA Controller

FIGURE 4-1:

TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS

CPU

SRAM

DMA RAM

CPU Peripheral DS Bus

Peripheral 3

DMA

Peripheral

Non-DMA

SRAM X-Bus

PORT 2

PORT 1

Peripheral 1

DMA

Ready

Peripheral 2

DMA

Ready

DMA DS Bus

CPU

DMA

CPU

DMA

CPU

DMA

Peripheral Indirect Address

Note: CPU and DMA address buses are not shown for clarity.

DMA Controller

Channels

DMA

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