33FJ128GP708 datasheet(24/90 Pages) MICROCHIP

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dsPIC33F

DS70155C-page 22

Preliminary

7.0

DEVICE POWER MANAGEMENT

Power

management

services

provided

the

dsPIC33F devices include:

• Real-Time Clock Source Switching

• Power-Saving Modes

7.1

Real-Time Clock Source Switching

Configuration bits determine the clock source upon

Power-on Reset (POR) and Brown-out Reset (BOR).

Thereafter, the clock source can be changed between

permissible clock sources. The OSCCON register

controls the clock switching and reflects system clock

related status bits. To reduce power consumption, the

user can switch to a slower clock source.

7.2

Power-Saving Modes

The dsPIC33F devices have two reduced power

modes that can be entered through execution of the

PWRSAV

instruction.

• Sleep Mode: The CPU, system clock source and

any peripherals that operate on the system clock

source are disabled. This is the lowest power

mode of the device.

• Idle Mode: The CPU is disabled but the system

clock source continues to operate. Peripherals

continue to operate but can optionally be disabled.

• Doze Mode: The CPU clock is temporarily slowed

down relative to the peripheral clock by a

user-selectable factor.

These modes provide an effective way to reduce power

consumption during periods when the CPU is not in use.

7.2.1

SLEEP MODE

When the device enters Sleep mode:

• System clock source is shut down. If an on-chip

oscillator is used, it is turned off.

• Device current consumption is at minimum

provided that no I/O pin is sourcing current.

• Fail-Safe Clock Monitor (FSCM) does not operate

during Sleep mode because the system clock

source is disabled.

• LPRC clock continues to run in Sleep mode if the

WDT is enabled.

• BOR circuit, if enabled, remains operative during

Sleep mode

• WDT, if enabled, is automatically cleared prior to

entering Sleep mode.

• Some peripherals may continue to operate in

Sleep mode. These peripherals include I/O pins

that detect a change in the input signal, or

peripherals that use an external clock input. Any

peripheral that is operating on the system clock

source is disabled in Sleep mode.

The processor exits (wakes up) from Sleep on one of

these events:

• Any interrupt source that is individually enabled

• Any form of device Reset

• A WDT time-out

7.2.2

IDLE MODE

When the device enters Idle mode:

• CPU stops executing instructions

• WDT is automatically cleared

• System clock source remains active

• Peripheral modules, by default, continue to

operate normally from the system clock source

• Peripherals, optionally, can be shut down in Idle

mode using their ‘stop-in-idle’ control bit.

• If the WDT or FSCM is enabled, the LPRC also

remains active

The processor wakes from Idle mode on these events:

• Any interrupt that is individually enabled

• Any source of device Reset

• A WDT time-out

Upon wake-up from Idle, the clock is re-applied to the

CPU and instruction execution begins immediately

starting with the instruction following the PWRSAV

instruction, or the first instruction in the Interrupt

Service Routine (ISR).

7.2.3

DOZE MODE

The Doze mode provides the user software the ability

to temporarily reduce the processor instruction cycle

frequency relative to the peripheral frequency. Clock

frequency ratios of 1:1, 1:2, 1:4, 1:8, 1:16, 1:32, 1:64

and 1:128 are supported.

For example, suppose the device is operating at

20 MIPS and the CAN module has been configured for

500 kbps bit rate based on this device operating speed.

If the device is now placed in Doze mode with a clock

frequency ratio of 1:4, the CAN module will continue to

communicate at the required bit rate of 500 kbps, but

the CPU now starts executing instructions at a

frequency of 5 MIPS.

This feature further reduces the power consumption

during periods where relatively less CPU activity is

required.

When the device is operating in Doze mode, the

hardware

ensures

that

there

loss

synchronization between peripheral events and SFR

accesses by the CPU.

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