33FJ128GP708 datasheet(9/90 Pages) MICROCHIP

9 / 90 page

Preliminary

DS70155C-page 7

dsPIC33F

3.0

CPU ARCHITECTURE

3.1

Overview

The dsPIC33F CPU module has a 16-bit (data)

modified Harvard architecture with an enhanced

instruction set, including significant support for DSP.

The CPU has a 24-bit instruction word with a variable

length opcode field. The Program Counter (PC) is

23 bits wide and addresses up to 4M x 24 bits of user

program memory space. The actual amount of program

memory implemented, as illustrated in Figure 3-1,

varies from one device to another. A single-cycle

instruction prefetch mechanism is used to help

maintain

throughput

and

provides

predictable

execution. All instructions execute in a single cycle,

with the exception of instructions that change the

program

flow,

the

double

word

move

(MOV.D)

instruction and the table instructions. Overhead-free

program loop constructs are supported using the DO

and

REPEAT

instructions,

both

which

are

interruptible at any point.

The dsPIC33F devices have sixteen 16-bit working

registers in the programmer’s model. Each of the

working registers can serve as a data, address or

address offset register. The 16th working register

(W15) operates as a software Stack Pointer (SP) for

interrupts and calls.

The dsPIC33F instruction set has two classes of

instructions: the MCU class of instructions and the DSP

class of instructions. These two instruction classes are

seamlessly

integrated

into

single

CPU.

The

instruction set includes many addressing modes and is

designed for optimum C compiler efficiency.

3.1.1

DATA MEMORY OVERVIEW

The data space can be addressed as 32K words or

64 Kbytes and is split into two blocks, referred to as X

and Y data memory. Each memory block has its own

independent Address Generation Unit (AGU). The

MCU class of instructions operates solely through the

X memory AGU, which accesses the entire memory

map as one linear data space. Certain DSP instructions

operate through the X and Y AGUs to support dual

operand reads, which splits the data address space

into two parts. The X and Y data space boundary is

device specific.

The upper 32 Kbytes of the data space memory map

can optionally be mapped into program space at any

16K program word boundary defined by the 8-bit

Program Space Visibility Page (PSVPAG) register. The

program-to-data space mapping feature lets any

instruction access program space as if it were data

space.

The data space includes 2 Kbytes of DMA RAM, which

is primarily used for DMA data transfers, but may be

used as general purpose RAM.

FIGURE 3-1:

PROGRAM SPACE

MEMORY MAP

Reset – Target Address

000000

0000FE

Reserved

000002

000100

Device Configuration

User Flash

Program Memory

02AC00

02ABFE

Osc. Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

DMA Error Vector

Reserved Vector

Interrupt Vector Table

(87296 x 24-bit)

800000

F80000

Registers (12 x 8-bit)

F80016

F80018

FFFFFE

F7FFFE

Reserved

000014

Reset – GOTO Instruction

000004

Reserved

7FFFFE

Reserved

000200

0001FE

000104

Alternate Vector Table

Reserved

Reserved Vector

Device ID (2 x 16-bit)

Reserved

FEFFFE

FF0000

FF0002

FF0004

33FJ128GP708 数据表(PDF) 9 Page - Microchip Technology

33FJ128GP708 数据表(HTML) 9 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

数据表下载

链接网址

33FJ128GP708 数据表(PDF) 9 Page - Microchip Technology

33FJ128GP708 数据表(HTML) 9 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

数据表 下载

链接网址

数据表下载